From b555941a3d06c31e03ecf51eef608c7356bdb3b9 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Mon, 29 Apr 2019 14:50:24 -0700 Subject: Update BSPs for platform header Signed-off-by: Nathaniel Graff --- bsp/sifive-hifive-unleashed/metal.h | 46 +++++++++++++++++++------------------ 1 file changed, 24 insertions(+), 22 deletions(-) (limited to 'bsp/sifive-hifive-unleashed/metal.h') diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h index b7a329b..118bdd3 100644 --- a/bsp/sifive-hifive-unleashed/metal.h +++ b/bsp/sifive-hifive-unleashed/metal.h @@ -3,6 +3,8 @@ #ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_H #define SIFIVE_HIFIVE_UNLEASHED__METAL_H +#include + #ifdef __METAL_MACHINE_MACROS #define __METAL_CLINT_NUM_PARENTS 10 @@ -192,7 +194,7 @@ struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000; struct __metal_driver_fixed_clock __metal_dt_refclk = { .vtable = &__metal_driver_vtable_fixed_clock, .clock.vtable = &__metal_driver_vtable_fixed_clock.clock, - .rate = 33333333UL, + .rate = METAL_FIXED_CLOCK__CLOCK_FREQUENCY, }; /* From tlclk */ @@ -201,8 +203,8 @@ struct __metal_driver_fixed_factor_clock __metal_dt_tlclk = { .clock.vtable = &__metal_driver_vtable_fixed_factor_clock.clock, /* From refclk */ .parent = &__metal_dt_refclk.clock, - .mult = 1, - .div = 2, + .mult = METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT, + .div = METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV, }; struct metal_memory __metal_dt_mem_dtim_1000000 = { @@ -317,8 +319,8 @@ struct metal_memory __metal_dt_mem_spi_10050000 = { struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { .vtable = &__metal_driver_vtable_riscv_clint0, .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable, - .control_base = 33554432UL, - .control_size = 65536UL, + .control_base = METAL_RISCV_CLINT0_2000000_BASE_ADDRESS, + .control_size = METAL_RISCV_CLINT0_2000000_SIZE, .init_done = 0, .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, @@ -446,24 +448,24 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .interrupt_lines[7] = 11, .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller, .interrupt_lines[8] = 9, - .control_base = 201326592UL, - .control_size = 67108864UL, - .max_priority = 7UL, - .num_interrupts = 54UL, + .control_base = METAL_RISCV_PLIC0_C000000_BASE_ADDRESS, + .control_size = METAL_RISCV_PLIC0_C000000_SIZE, + .max_priority = METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY, + .num_interrupts = METAL_RISCV_PLIC0_C000000_RISCV_NDEV, .interrupt_controller = 1, }; /* From pmp@0 */ struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = 1UL, + .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, }; /* From gpio@10060000 */ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = { .vtable = &__metal_driver_vtable_sifive_gpio0, .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio, - .base = 268828672UL, - .size = 4096UL, + .base = METAL_SIFIVE_GPIO0_10060000_BASE_ADDRESS, + .size = METAL_SIFIVE_GPIO0_10060000_SIZE, /* From interrupt_controller@c000000 */ .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, .num_interrupts = METAL_MAX_GPIO_INTERRUPTS, @@ -489,8 +491,8 @@ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = { struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = { .vtable = &__metal_driver_vtable_sifive_spi0, .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, - .control_base = 268697600UL, - .control_size = 4096UL, + .control_base = METAL_SIFIVE_SPI0_10040000_BASE_ADDRESS, + .control_size = METAL_SIFIVE_SPI0_10040000_SIZE, /* From tlclk */ .clock = &__metal_dt_tlclk.clock, .pinmux = NULL, @@ -500,8 +502,8 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = { struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = { .vtable = &__metal_driver_vtable_sifive_spi0, .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, - .control_base = 268701696UL, - .control_size = 4096UL, + .control_base = METAL_SIFIVE_SPI0_10041000_BASE_ADDRESS, + .control_size = METAL_SIFIVE_SPI0_10041000_SIZE, /* From tlclk */ .clock = &__metal_dt_tlclk.clock, .pinmux = NULL, @@ -511,8 +513,8 @@ struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = { struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000 = { .vtable = &__metal_driver_vtable_sifive_spi0, .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, - .control_base = 268763136UL, - .control_size = 4096UL, + .control_base = METAL_SIFIVE_SPI0_10050000_BASE_ADDRESS, + .control_size = METAL_SIFIVE_SPI0_10050000_SIZE, /* From tlclk */ .clock = &__metal_dt_tlclk.clock, .pinmux = NULL, @@ -530,8 +532,8 @@ struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = { .vtable = &__metal_driver_vtable_sifive_uart0, .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, - .control_base = 268500992UL, - .control_size = 4096UL, + .control_base = METAL_SIFIVE_UART0_10010000_BASE_ADDRESS, + .control_size = METAL_SIFIVE_UART0_10010000_SIZE, /* From tlclk */ .clock = &__metal_dt_tlclk.clock, .pinmux = NULL, @@ -545,8 +547,8 @@ struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = { struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000 = { .vtable = &__metal_driver_vtable_sifive_uart0, .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, - .control_base = 268505088UL, - .control_size = 4096UL, + .control_base = METAL_SIFIVE_UART0_10011000_BASE_ADDRESS, + .control_size = METAL_SIFIVE_UART0_10011000_SIZE, /* From tlclk */ .clock = &__metal_dt_tlclk.clock, .pinmux = NULL, -- cgit v1.2.1-18-gbd029