From 4be70b922c864c682135d5c66743b6b4c6a51c8f Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 4 Apr 2019 09:59:15 -0700 Subject: Add HiFive Unleashed board files Includes: - design.dts (including nodes for Vera board hardware) - openocd.cfg - settings.mk - README.md Signed-off-by: Nathaniel Graff --- bsp/sifive-hifive-unleashed/README.md | 19 + bsp/sifive-hifive-unleashed/design.dts | 622 ++++++++++++++++++++++++++++++++ bsp/sifive-hifive-unleashed/openocd.cfg | 24 ++ bsp/sifive-hifive-unleashed/settings.mk | 5 + 4 files changed, 670 insertions(+) create mode 100644 bsp/sifive-hifive-unleashed/README.md create mode 100644 bsp/sifive-hifive-unleashed/design.dts create mode 100644 bsp/sifive-hifive-unleashed/openocd.cfg create mode 100644 bsp/sifive-hifive-unleashed/settings.mk (limited to 'bsp/sifive-hifive-unleashed') diff --git a/bsp/sifive-hifive-unleashed/README.md b/bsp/sifive-hifive-unleashed/README.md new file mode 100644 index 0000000..1349a86 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/README.md @@ -0,0 +1,19 @@ +# SiFive HiFive Unleashed + +The SiFive HiFive Unleashed features an FU540-C000 SoC with the U54-MC Core IP. + +## Configuring MSEL + +The mode select switches should be set as follows: +``` + USB LED Mode Select Ethernet + +===|___|==****==+-+-+-+-+-+-+=================|******|===+ + | | | | |X|X|X| | | | + | | | | | | | | | | | + | HFXSEL->|X|X|X| | | | |______| | + | +-+-+-+-+-+-+ | + | RTCSEL-----/ 0 1 2 3 <--MSEL | + | | +``` + +This will cause the board to boot from the SPI flash at 0x2000\_0000. diff --git a/bsp/sifive-hifive-unleashed/design.dts b/bsp/sifive-hifive-unleashed/design.dts new file mode 100644 index 0000000..ddad3e2 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/design.dts @@ -0,0 +1,622 @@ +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,fu540g", "sifive,fu500"; + model = "sifive,hifive-unleashed-a00"; + + aliases { + serial0 = &L28; + serial1 = &L29; + }; + + chosen { + }; + + firmware { + sifive,fsbl = "YYYY-MM-DD"; + }; + + L3: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <1000000>; + L9: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + next-level-cache = <&L24 &L0>; + reg = <0>; + riscv,isa = "rv64imac"; + sifive,dtim = <&L8>; + sifive,itim = <&L7>; + status = "okay"; + L10: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L12: cpu@1 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <1>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L11>; + status = "okay"; + tlb-split; + L13: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L15: cpu@2 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <2>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L14>; + status = "okay"; + tlb-split; + L16: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L18: cpu@3 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <3>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L17>; + status = "okay"; + tlb-split; + L19: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + L21: cpu@4 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + next-level-cache = <&L24 &L0>; + reg = <4>; + riscv,isa = "rv64imafdc"; + sifive,itim = <&L20>; + status = "okay"; + tlb-split; + L22: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L36: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1f 0x80000000>; + }; + L2: soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus"; + ranges; + refclk: refclk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "xtal"; + }; + prci: prci@10000000 { + compatible = "sifive,ux00prci0"; + reg = <0x0 0x10000000 0x0 0x1000>; + reg-names = "control"; + clocks = <&refclk>; + #clock-cells = <1>; + }; + tlclk: tlclk { + compatible = "fixed-factor-clock"; + clocks = <&prci 0>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + L51: cadence-gemgxl-mgmt@100a0000 { + compatible = "sifive,cadencegemgxlmgmt0"; + reg = <0x0 0x100a0000 0x0 0x1000>; + reg-names = "control"; + #clock-cells = <0>; + }; + L35: bus-blocker@100b8000 { + compatible = "sifive,bus-blocker0"; + reg = <0x0 0x100b8000 0x0 0x1000>; + reg-names = "control"; + }; + L0: cache-controller@2010000 { + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <2048>; + cache-size = <2097152>; + cache-unified; + compatible = "sifive,ccache0", "cache"; + interrupt-parent = <&L4>; + interrupts = <1 2 3>; + next-level-cache = <&L25 &L40 &L36>; + reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x2000000>; + reg-names = "control", "sideband"; + }; + L33: cadence-ddr-mgmt@100c0000 { + compatible = "sifive,cadenceddrmgmt0"; + reg = <0x0 0x100c0000 0x0 0x1000>; + reg-names = "control"; + }; + L40: chiplink@40000000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "sifive,chiplink", "simple-bus"; + ranges = <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000 0x30 0x0 0x30 0x0 0x10 0x0 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x20 0x0 0x20 0x0 0x10 0x0>; + }; + L5: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L10 3 &L10 7 &L13 3 &L13 7 &L16 3 &L16 7 &L19 3 &L19 7 &L22 3 &L22 7>; + reg = <0x0 0x2000000 0x0 0x10000>; + reg-names = "control"; + }; + L6: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L10 65535 &L13 65535 &L16 65535 &L19 65535 &L22 65535>; + reg = <0x0 0x0 0x0 0x1000>; + reg-names = "control"; + }; + L32: dma@3000000 { + #dma-cells = <1>; + compatible = "riscv,dma0"; + dma-channels = <4>; + dma-requests = <0>; + interrupt-parent = <&L4>; + interrupts = <23 24 25 26 27 28 29 30>; + reg = <0x0 0x3000000 0x0 0x100000>; + reg-names = "control"; + riscv,dma-pools = <1>; + }; + L8: dtim@1000000 { + compatible = "sifive,dtim0"; + reg = <0x0 0x1000000 0x0 0x2000>; + reg-names = "mem"; + }; + L44: ememoryotp@10070000 { + compatible = "sifive,ememoryotp0"; + reg = <0x0 0x10070000 0x0 0x1000>; + reg-names = "control"; + }; + L24: error-device@18000000 { + compatible = "sifive,error0"; + reg = <0x0 0x18000000 0x0 0x8000000>; + reg-names = "mem"; + }; + L52: ethernet@10090000 { + compatible = "cdns,macb"; + interrupt-parent = <&L4>; + interrupts = <53>; + reg = <0x0 0x10090000 0x0 0x2000>; + reg-names = "control"; + + local-mac-address = [00 00 00 00 00 00]; + phy-mode = "gmii"; + clock-names = "pclk", "hclk", "tx_clk"; + clocks = <&prci 1>, <&prci 1>, <&L51>; + + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&L31 12 1>; + }; + }; + L31: gpio@10060000 { + compatible = "sifive,gpio0"; + interrupt-parent = <&L4>; + interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>; + reg = <0x0 0x10060000 0x0 0x1000>; + reg-names = "control"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&L31 10 1>; + }; + L47: i2c@10030000 { + compatible = "sifive,i2c0", "opencores,i2c-ocores"; + reg = <0x0 0x10030000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + + reg-shift = <2>; + reg-io-width = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + /* On pre-production boards only */ +/* + ina233-vdd_soc_core@40 { + compatible = "ti,pmbus"; + reg = <0x40>; + }; + ina233-vdd_ddr_soc@44 { + compatible = "ti,pmbus"; + reg = <0x44>; + }; + ina233-vdd_ddr_mem@45 { + compatible = "ti,pmbus"; + reg = <0x45>; + }; + ina233-vdd_corepll@47 { + compatible = "ti,pmbus"; + reg = <0x47>; + }; + ina233-vdd_otp@4a { + compatible = "ti,pmbus"; + reg = <0x4a>; + }; + ina233-vdd_io@4b { + compatible = "ti,pmbus"; + reg = <0x4b>; + }; + ina233-vdd_ddrpll@48 { + compatible = "ti,pmbus"; + reg = <0x48>; + }; + ina233-avdd_ddrpll@49 { + compatible = "ti,pmbus"; + reg = <0x49>; + }; + ina233-vdd_givdd@4c { + compatible = "ti,pmbus"; + reg = <0x4c>; + }; + ina233vdd_gemgxlpll@4d { + compatible = "ti,pmbus"; + reg = <0x4d>; + }; +*/ + /* On the tester board */ +/* + m24c02 { + compatible = "st,24c02"; + reg = <0x51>; + }; +*/ + }; + L4: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L10 11 &L13 11 &L13 9 &L16 11 &L16 9 &L19 11 &L19 9 &L22 11 &L22 9>; + reg = <0x0 0xc000000 0x0 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <53>; + }; + L7: itim@1800000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1800000 0x0 0x4000>; + reg-names = "mem"; + }; + L11: itim@1808000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1808000 0x0 0x8000>; + reg-names = "mem"; + }; + L14: itim@1810000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1810000 0x0 0x8000>; + reg-names = "mem"; + }; + L17: itim@1818000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1818000 0x0 0x8000>; + reg-names = "mem"; + }; + L20: itim@1820000 { + compatible = "sifive,itim0"; + reg = <0x0 0x1820000 0x0 0x8000>; + reg-names = "mem"; + }; + L37: memory-controller@100b0000 { + compatible = "sifive,ux00ddr0"; + interrupt-parent = <&L4>; + interrupts = <31>; + reg = <0x0 0x100b0000 0x0 0x4000>; + reg-names = "control"; + }; + pci@2000000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "xlnx,axi-pcie-host-1.00.a"; + device_type = "pci"; + interrupt-map = <0 0 0 1 &xil_pcie_intc 1 0 0 0 2 &xil_pcie_intc 2 0 0 0 3 &xil_pcie_intc 3 0 0 0 4 &xil_pcie_intc 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&L4>; + interrupts = <32>; + ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; + reg = <0x020 0x0 0x0 0x4000000>; + reg-names = "control"; + xil_pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + pci@2030000000 { + #address-cells = <3>; + #interrupt-cells = <1>; + #size-cells = <2>; + compatible = "ms-pf,axi-pcie-host"; + device_type = "pci"; + bus-range = <0x01 0x7f>; + interrupt-map = <0 0 0 1 &ms_pcie_intc 1 0 0 0 2 &ms_pcie_intc 2 0 0 0 3 &ms_pcie_intc 3 0 0 0 4 &ms_pcie_intc 4>; + interrupt-map-mask = <0 0 0 7>; + interrupt-parent = <&L4>; + interrupts = <32>; + ranges = <0x2000000 0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>; + reg = <0x20 0x30000000 0x0 0x4000000 0x20 0x0 0x0 0x100000>; + reg-names = "control", "apb"; + ms_pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + L53: pinctrl@10080000 { + compatible = "sifive,pinctrl0"; + reg = <0x0 0x10080000 0x0 0x1000>; + reg-names = "control"; + }; + L45: pwm@10020000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&L4>; + interrupts = <42 43 44 45>; + reg = <0x0 0x10020000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + sifive,approx-period = <1000000>; + #pwm-cells = <2>; + }; + L46: pwm@10021000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&L4>; + interrupts = <46 47 48 49>; + reg = <0x0 0x10021000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + sifive,approx-period = <1000000>; + #pwm-cells = <2>; + }; + pwmleds { + compatible = "pwm-leds"; + heartbeat { + pwms = <&L45 0 0>; + max-brightness = <255>; + linux,default-trigger = "heartbeat"; + }; + mtd { + pwms = <&L45 1 0>; + max-brightness = <255>; + linux,default-trigger = "mtd"; + }; + netdev { + pwms = <&L45 2 0>; + max-brightness = <255>; + linux,default-trigger = "netdev"; + }; + panic { + pwms = <&L45 3 0>; + max-brightness = <255>; + linux,default-trigger = "panic"; + }; + /* These LEDs are on the tester board */ +/* + testled { + pwms = <&L46 0 0>; + max-brightness = <255>; + }; + green { + pwms = <&L46 1 0>; + max-brightness = <255>; + }; + red { + pwms = <&L46 2 0>; + max-brightness = <255>; + }; + blue { + pwms = <&L46 3 0>; + max-brightness = <255>; + }; +*/ + }; + L27: rom@1000 { + compatible = "sifive,modeselect0"; + reg = <0x0 0x1000 0x0 0x1000>; + reg-names = "mem"; + }; + L26: rom@10000 { + compatible = "sifive,maskrom0"; + reg = <0x0 0x10000 0x0 0x8000>; + reg-names = "mem"; + }; + L25: rom@a000000 { + compatible = "ucbbar,cacheable-zero0"; + reg = <0x0 0xa000000 0x0 0x2000000>; + reg-names = "mem"; + }; + L28: serial@10010000 { + compatible = "sifive,uart0"; + interrupt-parent = <&L4>; + interrupts = <4>; + reg = <0x0 0x10010000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + }; + L29: serial@10011000 { + compatible = "sifive,uart0"; + interrupt-parent = <&L4>; + interrupts = <5>; + reg = <0x0 0x10011000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + }; + L49: spi@10040000 { + compatible = "sifive,spi0"; + interrupt-parent = <&L4>; + interrupts = <51>; + reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; + reg-names = "control", "mem"; + clocks = <&tlclk>; + + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "issi,is25wp256d", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <50000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + }; + L50: spi@10041000 { + compatible = "sifive,spi0"; + interrupt-parent = <&L4>; + interrupts = <52>; + reg = <0x0 0x10041000 0x0 0x1000 0x0 0x30000000 0x0 0x10000000>; + reg-names = "control", "mem"; + clocks = <&tlclk>; + + #address-cells = <1>; + #size-cells = <0>; + + /* These flash chips are on the tester board */ +/* + flash@0 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + flash@1 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <1>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + flash@2 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <2>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; + flash@3 { + compatible = "issi,is25wp032", "jedec,spi-nor"; + reg = <3>; + spi-max-frequency = <25000000>; + m25p,fast-read; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +*/ + }; + L30: spi@10050000 { + compatible = "sifive,spi0"; + interrupt-parent = <&L4>; + interrupts = <6>; + reg = <0x0 0x10050000 0x0 0x1000>; + reg-names = "control"; + clocks = <&tlclk>; + + #address-cells = <1>; + #size-cells = <0>; + mmc@0 { + compatible = "mmc-spi-slot"; + reg = <0>; + spi-max-frequency = <20000000>; + voltage-ranges = <3300 3300>; + disable-wp; + gpios = <&L31 11 1>; + }; + }; + L23: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x0 0x4000 0x0 0x1000>; + reg-names = "control"; + }; + }; +}; diff --git a/bsp/sifive-hifive-unleashed/openocd.cfg b/bsp/sifive-hifive-unleashed/openocd.cfg new file mode 100644 index 0000000..7589897 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/openocd.cfg @@ -0,0 +1,24 @@ +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Dual RS232-HS" +ftdi_vid_pid 0x0403 0x6010 + +ftdi_layout_init 0x0008 0x001b +ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME -rtos riscv +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank onboard_spi_flash fespi 0x20000000 0 0 0 $_TARGETNAME 0x10040000 +init +halt + +# Uncomment this if you want to be able to clobber your SPI Flash, which +# probably you don't since you can do it through Linux + +# flash protect 0 0 last off diff --git a/bsp/sifive-hifive-unleashed/settings.mk b/bsp/sifive-hifive-unleashed/settings.mk new file mode 100644 index 0000000..38a72d6 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/settings.mk @@ -0,0 +1,5 @@ +RISCV_ARCH=rv64imac +RISCV_ABI=lp64 +RISCV_CMODEL=medany + +TARGET_TAGS=board openocd -- cgit v1.2.1-18-gbd029 From c75d52d67bfa1568d6ac490224bae44d808b7d52 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 4 Apr 2019 14:49:56 -0700 Subject: Fixup HiFive Unleashed design.dts - Add stdout-path - Add PMP node - Point tlclk at refclk instead of PRCI Signed-off-by: Nathaniel Graff --- bsp/sifive-hifive-unleashed/design.dts | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) (limited to 'bsp/sifive-hifive-unleashed') diff --git a/bsp/sifive-hifive-unleashed/design.dts b/bsp/sifive-hifive-unleashed/design.dts index ddad3e2..ee6897f 100644 --- a/bsp/sifive-hifive-unleashed/design.dts +++ b/bsp/sifive-hifive-unleashed/design.dts @@ -12,6 +12,7 @@ }; chosen { + stdout-path = "/soc/serial@10010000:115200"; }; firmware { @@ -159,6 +160,10 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus"; ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <1>; + }; refclk: refclk { #clock-cells = <0>; compatible = "fixed-clock"; @@ -174,7 +179,7 @@ }; tlclk: tlclk { compatible = "fixed-factor-clock"; - clocks = <&prci 0>; + clocks = <&refclk>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; -- cgit v1.2.1-18-gbd029 From 02dc7f4f76e4f6c2cb31207b14f261fec49f98ce Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Wed, 3 Apr 2019 12:50:13 -0700 Subject: Update BSPs for Unleashed and U54(MC) Signed-off-by: Nathaniel Graff --- bsp/sifive-hifive-unleashed/metal.default.lds | 231 ++++++++ bsp/sifive-hifive-unleashed/metal.h | 647 +++++++++++++++++++++++ bsp/sifive-hifive-unleashed/metal.ramrodata.lds | 228 ++++++++ bsp/sifive-hifive-unleashed/metal.scratchpad.lds | 231 ++++++++ 4 files changed, 1337 insertions(+) create mode 100644 bsp/sifive-hifive-unleashed/metal.default.lds create mode 100644 bsp/sifive-hifive-unleashed/metal.h create mode 100644 bsp/sifive-hifive-unleashed/metal.ramrodata.lds create mode 100644 bsp/sifive-hifive-unleashed/metal.scratchpad.lds (limited to 'bsp/sifive-hifive-unleashed') diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds new file mode 100644 index 0000000..61b2203 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/metal.default.lds @@ -0,0 +1,231 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x80000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 + flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 0x10000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_NULL; + itim PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >flash AT>flash :flash + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >flash AT>flash :flash + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>flash :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>flash :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >flash AT>flash :flash + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>flash :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + . = __stack_size; + . = __stack_size; + . = __stack_size; + . = __stack_size; + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h new file mode 100644 index 0000000..b7a329b --- /dev/null +++ b/bsp/sifive-hifive-unleashed/metal.h @@ -0,0 +1,647 @@ +#ifndef ASSEMBLY + +#ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_H +#define SIFIVE_HIFIVE_UNLEASHED__METAL_H + +#ifdef __METAL_MACHINE_MACROS + +#define __METAL_CLINT_NUM_PARENTS 10 + +#ifndef __METAL_CLINT_NUM_PARENTS +#define __METAL_CLINT_NUM_PARENTS 0 +#endif +#define __METAL_PLIC_SUBINTERRUPTS 54 + +#define __METAL_PLIC_NUM_PARENTS 9 + +#ifndef __METAL_PLIC_SUBINTERRUPTS +#define __METAL_PLIC_SUBINTERRUPTS 0 +#endif +#ifndef __METAL_PLIC_NUM_PARENTS +#define __METAL_PLIC_NUM_PARENTS 0 +#endif +#ifndef __METAL_CLIC_SUBINTERRUPTS +#define __METAL_CLIC_SUBINTERRUPTS 0 +#endif + +#else /* ! __METAL_MACHINE_MACROS */ + +#define __METAL_CLINT_2000000_INTERRUPTS 10 + +#define METAL_MAX_CLINT_INTERRUPTS 10 + +#define __METAL_CLINT_NUM_PARENTS 10 + +#define __METAL_INTERRUPT_CONTROLLER_C000000_INTERRUPTS 9 + +#define __METAL_PLIC_SUBINTERRUPTS 54 + +#define METAL_MAX_PLIC_INTERRUPTS 9 + +#define __METAL_PLIC_NUM_PARENTS 9 + +#define __METAL_CLIC_SUBINTERRUPTS 0 +#define METAL_MAX_CLIC_INTERRUPTS 0 + +#define METAL_MAX_LOCAL_EXT_INTERRUPTS 0 + +#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 0 + +#define __METAL_GPIO_10060000_INTERRUPTS 16 + +#define METAL_MAX_GPIO_INTERRUPTS 16 + +#define __METAL_SERIAL_10010000_INTERRUPTS 1 + +#define __METAL_SERIAL_10011000_INTERRUPTS 1 + +#define METAL_MAX_UART_INTERRUPTS 1 + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* From refclk */ +asm (".weak __metal_dt_refclk"); +struct __metal_driver_fixed_clock __metal_dt_refclk; + +/* From tlclk */ +asm (".weak __metal_dt_tlclk"); +struct __metal_driver_fixed_factor_clock __metal_dt_tlclk; + +asm (".weak __metal_dt_mem_dtim_1000000"); +struct metal_memory __metal_dt_mem_dtim_1000000; + +asm (".weak __metal_dt_mem_itim_1800000"); +struct metal_memory __metal_dt_mem_itim_1800000; + +asm (".weak __metal_dt_mem_itim_1808000"); +struct metal_memory __metal_dt_mem_itim_1808000; + +asm (".weak __metal_dt_mem_itim_1810000"); +struct metal_memory __metal_dt_mem_itim_1810000; + +asm (".weak __metal_dt_mem_itim_1818000"); +struct metal_memory __metal_dt_mem_itim_1818000; + +asm (".weak __metal_dt_mem_itim_1820000"); +struct metal_memory __metal_dt_mem_itim_1820000; + +asm (".weak __metal_dt_mem_memory_80000000"); +struct metal_memory __metal_dt_mem_memory_80000000; + +asm (".weak __metal_dt_mem_spi_10040000"); +struct metal_memory __metal_dt_mem_spi_10040000; + +asm (".weak __metal_dt_mem_spi_10041000"); +struct metal_memory __metal_dt_mem_spi_10041000; + +asm (".weak __metal_dt_mem_spi_10050000"); +struct metal_memory __metal_dt_mem_spi_10050000; + +/* From clint@2000000 */ +asm (".weak __metal_dt_clint_2000000"); +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000; + +/* From cpu@0 */ +asm (".weak __metal_dt_cpu_0"); +struct __metal_driver_cpu __metal_dt_cpu_0; + +/* From cpu@1 */ +asm (".weak __metal_dt_cpu_1"); +struct __metal_driver_cpu __metal_dt_cpu_1; + +/* From cpu@2 */ +asm (".weak __metal_dt_cpu_2"); +struct __metal_driver_cpu __metal_dt_cpu_2; + +/* From cpu@3 */ +asm (".weak __metal_dt_cpu_3"); +struct __metal_driver_cpu __metal_dt_cpu_3; + +/* From cpu@4 */ +asm (".weak __metal_dt_cpu_4"); +struct __metal_driver_cpu __metal_dt_cpu_4; + +asm (".weak __metal_dt_cpu_0_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; + +asm (".weak __metal_dt_cpu_1_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller; + +asm (".weak __metal_dt_cpu_2_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller; + +asm (".weak __metal_dt_cpu_3_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller; + +asm (".weak __metal_dt_cpu_4_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller; + +/* From interrupt_controller@c000000 */ +asm (".weak __metal_dt_interrupt_controller_c000000"); +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; + +asm (".weak __metal_dt_pmp_0"); +struct metal_pmp __metal_dt_pmp_0; + +/* From gpio@10060000 */ +asm (".weak __metal_dt_gpio_10060000"); +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000; + +/* From spi@10040000 */ +asm (".weak __metal_dt_spi_10040000"); +struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000; + +/* From spi@10041000 */ +asm (".weak __metal_dt_spi_10041000"); +struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000; + +/* From spi@10050000 */ +asm (".weak __metal_dt_spi_10050000"); +struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000; + +/* From teststatus@4000 */ +asm (".weak __metal_dt_teststatus_4000"); +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; + +/* From serial@10010000 */ +asm (".weak __metal_dt_serial_10010000"); +struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000; + +/* From serial@10011000 */ +asm (".weak __metal_dt_serial_10011000"); +struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000; + +/* From cache_controller@2010000 */ +asm (".weak __metal_dt_cache_controller_2010000"); +struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000; + + +/* From refclk */ +struct __metal_driver_fixed_clock __metal_dt_refclk = { + .vtable = &__metal_driver_vtable_fixed_clock, + .clock.vtable = &__metal_driver_vtable_fixed_clock.clock, + .rate = 33333333UL, +}; + +/* From tlclk */ +struct __metal_driver_fixed_factor_clock __metal_dt_tlclk = { + .vtable = &__metal_driver_vtable_fixed_factor_clock, + .clock.vtable = &__metal_driver_vtable_fixed_factor_clock.clock, +/* From refclk */ + .parent = &__metal_dt_refclk.clock, + .mult = 1, + .div = 2, +}; + +struct metal_memory __metal_dt_mem_dtim_1000000 = { + ._base_address = 16777216UL, + ._size = 8192UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1800000 = { + ._base_address = 25165824UL, + ._size = 16384UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1808000 = { + ._base_address = 25198592UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1810000 = { + ._base_address = 25231360UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1818000 = { + ._base_address = 25264128UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_itim_1820000 = { + ._base_address = 25296896UL, + ._size = 32768UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_memory_80000000 = { + ._base_address = 2147483648UL, + ._size = 135291469824UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_10040000 = { + ._base_address = 536870912UL, + ._size = 268435456UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_10041000 = { + ._base_address = 805306368UL, + ._size = 268435456UL, + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +struct metal_memory __metal_dt_mem_spi_10050000 = { + ._attrs = { + .R = 1, + .W = 1, + .X = 1, + .C = 1, + .A = 1}, +}; + +/* From clint@2000000 */ +struct __metal_driver_riscv_clint0 __metal_dt_clint_2000000 = { + .vtable = &__metal_driver_vtable_riscv_clint0, + .controller.vtable = &__metal_driver_vtable_riscv_clint0.clint_vtable, + .control_base = 33554432UL, + .control_size = 65536UL, + .init_done = 0, + .num_interrupts = METAL_MAX_CLINT_INTERRUPTS, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 3, + .interrupt_parents[1] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[1] = 7, + .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[2] = 3, + .interrupt_parents[3] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[3] = 7, + .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[4] = 3, + .interrupt_parents[5] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[5] = 7, + .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[6] = 3, + .interrupt_parents[7] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[7] = 7, + .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[8] = 3, + .interrupt_parents[9] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[9] = 7, +}; + +/* From cpu@0 */ +struct __metal_driver_cpu __metal_dt_cpu_0 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_0_interrupt_controller.controller, +}; + +/* From cpu@1 */ +struct __metal_driver_cpu __metal_dt_cpu_1 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_1_interrupt_controller.controller, +}; + +/* From cpu@2 */ +struct __metal_driver_cpu __metal_dt_cpu_2 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_2_interrupt_controller.controller, +}; + +/* From cpu@3 */ +struct __metal_driver_cpu __metal_dt_cpu_3 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_3_interrupt_controller.controller, +}; + +/* From cpu@4 */ +struct __metal_driver_cpu __metal_dt_cpu_4 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_cpu_4_interrupt_controller.controller, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_1_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_2_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_3_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller@c000000 */ +struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { + .vtable = &__metal_driver_vtable_riscv_plic0, + .controller.vtable = &__metal_driver_vtable_riscv_plic0.plic_vtable, + .init_done = 0, + .interrupt_parents[0] = &__metal_dt_cpu_0_interrupt_controller.controller, + .interrupt_lines[0] = 11, + .interrupt_parents[1] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[1] = 11, + .interrupt_parents[2] = &__metal_dt_cpu_1_interrupt_controller.controller, + .interrupt_lines[2] = 9, + .interrupt_parents[3] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[3] = 11, + .interrupt_parents[4] = &__metal_dt_cpu_2_interrupt_controller.controller, + .interrupt_lines[4] = 9, + .interrupt_parents[5] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[5] = 11, + .interrupt_parents[6] = &__metal_dt_cpu_3_interrupt_controller.controller, + .interrupt_lines[6] = 9, + .interrupt_parents[7] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[7] = 11, + .interrupt_parents[8] = &__metal_dt_cpu_4_interrupt_controller.controller, + .interrupt_lines[8] = 9, + .control_base = 201326592UL, + .control_size = 67108864UL, + .max_priority = 7UL, + .num_interrupts = 54UL, + .interrupt_controller = 1, +}; + +/* From pmp@0 */ +struct metal_pmp __metal_dt_pmp_0 = { + .num_regions = 1UL, +}; + +/* From gpio@10060000 */ +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = { + .vtable = &__metal_driver_vtable_sifive_gpio0, + .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio, + .base = 268828672UL, + .size = 4096UL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_GPIO_INTERRUPTS, + .interrupt_lines[0] = 7, + .interrupt_lines[1] = 8, + .interrupt_lines[2] = 9, + .interrupt_lines[3] = 10, + .interrupt_lines[4] = 11, + .interrupt_lines[5] = 12, + .interrupt_lines[6] = 13, + .interrupt_lines[7] = 14, + .interrupt_lines[8] = 15, + .interrupt_lines[9] = 16, + .interrupt_lines[10] = 17, + .interrupt_lines[11] = 18, + .interrupt_lines[12] = 19, + .interrupt_lines[13] = 20, + .interrupt_lines[14] = 21, + .interrupt_lines[15] = 22, +}; + +/* From spi@10040000 */ +struct __metal_driver_sifive_spi0 __metal_dt_spi_10040000 = { + .vtable = &__metal_driver_vtable_sifive_spi0, + .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, + .control_base = 268697600UL, + .control_size = 4096UL, +/* From tlclk */ + .clock = &__metal_dt_tlclk.clock, + .pinmux = NULL, +}; + +/* From spi@10041000 */ +struct __metal_driver_sifive_spi0 __metal_dt_spi_10041000 = { + .vtable = &__metal_driver_vtable_sifive_spi0, + .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, + .control_base = 268701696UL, + .control_size = 4096UL, +/* From tlclk */ + .clock = &__metal_dt_tlclk.clock, + .pinmux = NULL, +}; + +/* From spi@10050000 */ +struct __metal_driver_sifive_spi0 __metal_dt_spi_10050000 = { + .vtable = &__metal_driver_vtable_sifive_spi0, + .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, + .control_base = 268763136UL, + .control_size = 4096UL, +/* From tlclk */ + .clock = &__metal_dt_tlclk.clock, + .pinmux = NULL, +}; + +/* From teststatus@4000 */ +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { + .vtable = &__metal_driver_vtable_sifive_test0, + .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown, + .base = 16384UL, + .size = 4096UL, +}; + +/* From serial@10010000 */ +struct __metal_driver_sifive_uart0 __metal_dt_serial_10010000 = { + .vtable = &__metal_driver_vtable_sifive_uart0, + .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, + .control_base = 268500992UL, + .control_size = 4096UL, +/* From tlclk */ + .clock = &__metal_dt_tlclk.clock, + .pinmux = NULL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_UART_INTERRUPTS, + .interrupt_line = 4UL, +}; + +/* From serial@10011000 */ +struct __metal_driver_sifive_uart0 __metal_dt_serial_10011000 = { + .vtable = &__metal_driver_vtable_sifive_uart0, + .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, + .control_base = 268505088UL, + .control_size = 4096UL, +/* From tlclk */ + .clock = &__metal_dt_tlclk.clock, + .pinmux = NULL, +/* From interrupt_controller@c000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_c000000.controller, + .num_interrupts = METAL_MAX_UART_INTERRUPTS, + .interrupt_line = 5UL, +}; + +/* From cache_controller@2010000 */ +struct __metal_driver_sifive_fu540_c000_l2 __metal_dt_cache_controller_2010000 = { + .vtable = &__metal_driver_vtable_sifive_fu540_c000_l2, + .cache.vtable = &__metal_driver_vtable_sifive_fu540_c000_l2.cache, +}; + + +#define __METAL_DT_MAX_MEMORIES 9 + +asm (".weak __metal_memory_table"); +struct metal_memory *__metal_memory_table[] = { + &__metal_dt_mem_dtim_1000000, + &__metal_dt_mem_itim_1800000, + &__metal_dt_mem_itim_1808000, + &__metal_dt_mem_itim_1810000, + &__metal_dt_mem_itim_1818000, + &__metal_dt_mem_itim_1820000, + &__metal_dt_mem_memory_80000000, + &__metal_dt_mem_spi_10040000, + &__metal_dt_mem_spi_10041000}; + +/* From serial@10010000 */ +#define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_10010000.uart) + +#define __METAL_DT_SERIAL_10010000_HANDLE (&__metal_dt_serial_10010000.uart) + +#define __METAL_DT_STDOUT_UART_BAUD 115200 + +/* From clint@2000000 */ +#define __METAL_DT_RISCV_CLINT0_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_CLINT_2000000_HANDLE (&__metal_dt_clint_2000000.controller) + +#define __METAL_DT_MAX_HARTS 5 + +asm (".weak __metal_cpu_table"); +struct __metal_driver_cpu *__metal_cpu_table[] = { + &__metal_dt_cpu_0, + &__metal_dt_cpu_1, + &__metal_dt_cpu_2, + &__metal_dt_cpu_3, + &__metal_dt_cpu_4}; + +/* From interrupt_controller@c000000 */ +#define __METAL_DT_RISCV_PLIC0_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) + +/* From pmp@0 */ +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) + +#define __MEE_DT_MAX_GPIOS 1 + +asm (".weak __metal_gpio_table"); +struct __metal_driver_sifive_gpio0 *__metal_gpio_table[] = { + &__metal_dt_gpio_10060000}; + +#define __METAL_DT_MAX_BUTTONS 0 + +asm (".weak __metal_button_table"); +struct __metal_driver_sifive_gpio_button *__metal_button_table[] = { + NULL }; +#define __METAL_DT_MAX_LEDS 0 + +asm (".weak __metal_led_table"); +struct __metal_driver_sifive_gpio_led *__metal_led_table[] = { + NULL }; +#define __METAL_DT_MAX_SWITCHES 0 + +asm (".weak __metal_switch_table"); +struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = { + NULL }; +#define __METAL_DT_MAX_SPIS 3 + +asm (".weak __metal_spi_table"); +struct __metal_driver_sifive_spi0 *__metal_spi_table[] = { + &__metal_dt_spi_10040000, + &__metal_dt_spi_10041000, + &__metal_dt_spi_10050000}; + +/* From teststatus@4000 */ +#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_teststatus_4000.shutdown) + +#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown) + + +#endif /* ! __METAL_MACHINE_MACROS */ +#endif /* SIFIVE_HIFIVE_UNLEASHED__METAL_H*/ +#endif /* ! ASSEMBLY */ diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds new file mode 100644 index 0000000..b57aaf7 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds @@ -0,0 +1,228 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x80000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 + flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 0x10000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_NULL; + itim PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >flash AT>flash :flash + + + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >flash AT>flash :flash + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>flash :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>flash :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >flash AT>flash :flash + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>flash :ram_init + + + .data : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + . = __stack_size; + . = __stack_size; + . = __stack_size; + . = __stack_size; + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds new file mode 100644 index 0000000..f145bc7 --- /dev/null +++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds @@ -0,0 +1,231 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x80000000 + itim (wx!rai) : ORIGIN = 0x1800000, LENGTH = 0x4000 + flash (rxai!w) : ORIGIN = 0x20000000, LENGTH = 0x10000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_LOAD; + itim PT_LOAD; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + PROVIDE(__stack_size = __stack_size); + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + KEEP (*(.text.libgloss.start)) + } >ram AT>ram :ram + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >ram AT>ram :ram + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >itim AT>ram :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>ram :itim_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >ram AT>ram :ram + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>ram :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.* .sdata2.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + . = __stack_size; + . = __stack_size; + . = __stack_size; + . = __stack_size; + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + -- cgit v1.2.1-18-gbd029