From b87018b8a5afa98a6f799527d9a4417290349a4a Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 21 May 2019 10:51:18 -0700 Subject: Modify BSP DTSs to use riscv,pmpregions property Signed-off-by: Nathaniel Graff --- bsp/sifive-hifive-unleashed/design.dts | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'bsp/sifive-hifive-unleashed') diff --git a/bsp/sifive-hifive-unleashed/design.dts b/bsp/sifive-hifive-unleashed/design.dts index ee6897f..8702be3 100644 --- a/bsp/sifive-hifive-unleashed/design.dts +++ b/bsp/sifive-hifive-unleashed/design.dts @@ -33,6 +33,7 @@ next-level-cache = <&L24 &L0>; reg = <0>; riscv,isa = "rv64imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L8>; sifive,itim = <&L7>; status = "okay"; @@ -60,6 +61,7 @@ next-level-cache = <&L24 &L0>; reg = <1>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L11>; status = "okay"; tlb-split; @@ -87,6 +89,7 @@ next-level-cache = <&L24 &L0>; reg = <2>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L14>; status = "okay"; tlb-split; @@ -114,6 +117,7 @@ next-level-cache = <&L24 &L0>; reg = <3>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L17>; status = "okay"; tlb-split; @@ -141,6 +145,7 @@ next-level-cache = <&L24 &L0>; reg = <4>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L20>; status = "okay"; tlb-split; @@ -160,10 +165,6 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu500-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <1>; - }; refclk: refclk { #clock-cells = <0>; compatible = "fixed-clock"; -- cgit v1.2.3