From 12485f45ebb7f96dc60951bf4365533652ac5139 Mon Sep 17 00:00:00 2001
From: Nathaniel Graff <nathaniel.graff@sifive.com>
Date: Thu, 23 May 2019 14:16:04 -0700
Subject: Update BSPs

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
---
 bsp/sifive-hifive1/metal-inline.h       |  2 +-
 bsp/sifive-hifive1/metal-platform.h     |  2 +-
 bsp/sifive-hifive1/metal.default.lds    |  3 ++-
 bsp/sifive-hifive1/metal.h              | 26 +++++++++++++-------------
 bsp/sifive-hifive1/metal.ramrodata.lds  |  3 ++-
 bsp/sifive-hifive1/metal.scratchpad.lds |  3 ++-
 bsp/sifive-hifive1/settings.mk          |  4 +++-
 7 files changed, 24 insertions(+), 19 deletions(-)

(limited to 'bsp/sifive-hifive1')

diff --git a/bsp/sifive-hifive1/metal-inline.h b/bsp/sifive-hifive1/metal-inline.h
index 10470c7..cf122a8 100644
--- a/bsp/sifive-hifive1/metal-inline.h
+++ b/bsp/sifive-hifive1/metal-inline.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-50        */
+/* [XXXXX] 28-05-2019 10-06-17        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
diff --git a/bsp/sifive-hifive1/metal-platform.h b/bsp/sifive-hifive1/metal-platform.h
index 0bda7f1..eaa722e 100644
--- a/bsp/sifive-hifive1/metal-platform.h
+++ b/bsp/sifive-hifive1/metal-platform.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-50        */
+/* [XXXXX] 28-05-2019 10-06-17        */
 /* ----------------------------------- */
 
 #ifndef SIFIVE_HIFIVE1__METAL_PLATFORM_H
diff --git a/bsp/sifive-hifive1/metal.default.lds b/bsp/sifive-hifive1/metal.default.lds
index 3b27dd0..e43ada6 100644
--- a/bsp/sifive-hifive1/metal.default.lds
+++ b/bsp/sifive-hifive1/metal.default.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-50        */
+/* [XXXXX] 28-05-2019 10-06-17        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 0);
 
 
 	.init 		:
diff --git a/bsp/sifive-hifive1/metal.h b/bsp/sifive-hifive1/metal.h
index 29f6127..b17884d 100644
--- a/bsp/sifive-hifive1/metal.h
+++ b/bsp/sifive-hifive1/metal.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-50        */
+/* [XXXXX] 28-05-2019 10-06-17        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
@@ -73,19 +73,19 @@
 
 #include <metal/drivers/fixed-clock.h>
 #include <metal/memory.h>
-#include <metal/drivers/riscv,clint0.h>
-#include <metal/drivers/riscv,cpu.h>
-#include <metal/drivers/riscv,plic0.h>
+#include <metal/drivers/riscv_clint0.h>
+#include <metal/drivers/riscv_cpu.h>
+#include <metal/drivers/riscv_plic0.h>
 #include <metal/pmp.h>
-#include <metal/drivers/sifive,local-external-interrupts0.h>
-#include <metal/drivers/sifive,gpio0.h>
-#include <metal/drivers/sifive,gpio-leds.h>
-#include <metal/drivers/sifive,spi0.h>
-#include <metal/drivers/sifive,uart0.h>
-#include <metal/drivers/sifive,fe310-g000,hfrosc.h>
-#include <metal/drivers/sifive,fe310-g000,hfxosc.h>
-#include <metal/drivers/sifive,fe310-g000,pll.h>
-#include <metal/drivers/sifive,fe310-g000,prci.h>
+#include <metal/drivers/sifive_local-external-interrupts0.h>
+#include <metal/drivers/sifive_gpio0.h>
+#include <metal/drivers/sifive_gpio-leds.h>
+#include <metal/drivers/sifive_spi0.h>
+#include <metal/drivers/sifive_uart0.h>
+#include <metal/drivers/sifive_fe310-g000_hfrosc.h>
+#include <metal/drivers/sifive_fe310-g000_hfxosc.h>
+#include <metal/drivers/sifive_fe310-g000_pll.h>
+#include <metal/drivers/sifive_fe310-g000_prci.h>
 
 /* From clock@0 */
 struct __metal_driver_fixed_clock __metal_dt_clock_0;
diff --git a/bsp/sifive-hifive1/metal.ramrodata.lds b/bsp/sifive-hifive1/metal.ramrodata.lds
index 2f49231..7a0c40d 100644
--- a/bsp/sifive-hifive1/metal.ramrodata.lds
+++ b/bsp/sifive-hifive1/metal.ramrodata.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-50        */
+/* [XXXXX] 28-05-2019 10-06-17        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 0);
 
 
 	.init 		:
diff --git a/bsp/sifive-hifive1/metal.scratchpad.lds b/bsp/sifive-hifive1/metal.scratchpad.lds
index cb27d7e..592e68c 100644
--- a/bsp/sifive-hifive1/metal.scratchpad.lds
+++ b/bsp/sifive-hifive1/metal.scratchpad.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-50        */
+/* [XXXXX] 28-05-2019 10-06-17        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 0);
 
 
 	.init 		:
diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk
index 6b305de..eedf871 100644
--- a/bsp/sifive-hifive1/settings.mk
+++ b/bsp/sifive-hifive1/settings.mk
@@ -1,12 +1,14 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 23-05-2019 13-29-50        #
+# [XXXXX] 28-05-2019 10-06-17        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imac
 RISCV_ABI=ilp32
 RISCV_CMODEL=medlow
+RISCV_SERIES=sifive-3-series
 
 TARGET_TAGS=board openocd
 TARGET_DHRY_ITERS=20000000
+TARGET_CORE_ITERS=5000
-- 
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