From 32214436b103438abf4018b34e6c29bb71522249 Mon Sep 17 00:00:00 2001
From: Nathaniel Graff <nathaniel.graff@sifive.com>
Date: Wed, 13 Feb 2019 15:50:42 -0800
Subject: Add clocking and pinmux to the SPI on hifive1

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
---
 bsp/sifive-hifive1/design.dts | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

(limited to 'bsp/sifive-hifive1')

diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts
index ff95ae0..5ddee6f 100644
--- a/bsp/sifive-hifive1/design.dts
+++ b/bsp/sifive-hifive1/design.dts
@@ -8,7 +8,7 @@
 
         chosen {
                 stdout-path = "/soc/serial@10013000:115200";
-                metal,entry = <&sip0 0x400000>;
+                metal,entry = <&spi0 0x400000>;
         };
 
         cpus {
@@ -22,7 +22,7 @@
                         i-cache-block-size = <64>;
                         i-cache-sets = <128>;
                         i-cache-size = <16384>;
-                        next-level-cache = <&sip0>;
+                        next-level-cache = <&spi0>;
                         reg = <0>;
                         riscv,isa = "rv32imac";
                         sifive,dtim = <&dtim>;
@@ -171,12 +171,14 @@
                         clocks = <&hfclk>;
                         pinmux = <&gpio0 0x30000 0x30000>;
                 };
-                sip0: spi@10014000 {
+                spi0: spi@10014000 {
                         compatible = "sifive,spi0";
                         interrupt-parent = <&plic>;
                         interrupts = <6>;
                         reg = <0x10014000 0x1000 0x20000000 0x20000000>;
                         reg-names = "control", "mem";
+                        clocks = <&hfclk>;
+                        pinmux = <&gpio0 0x0003C 0x0003C>;
                 };
         };
 };
-- 
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