From e18401806b38ca0f60394780191df4b72cb2f88a Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Mon, 25 Feb 2019 18:57:35 -0800 Subject: Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/sifive-hifive1/README.md | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 bsp/sifive-hifive1/README.md (limited to 'bsp/sifive-hifive1') diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md new file mode 100644 index 0000000..1cc077e --- /dev/null +++ b/bsp/sifive-hifive1/README.md @@ -0,0 +1,12 @@ +HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. + +his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 8 regions + - 16 local interrupts signal that can be connected to off core complex devices + - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels + - GPIO memory with 16 interrupt lines + - SPI memory with 1 intterupt line + - Serial port with 1 interrupt line + - 1 RGB LEDS -- cgit v1.2.3 From 2ee3eec227ca11e0355358aa553b4618fff50bd9 Mon Sep 17 00:00:00 2001 From: Kevin Mills Date: Tue, 26 Feb 2019 08:02:01 -0800 Subject: Add corrected formatting for bullet lists Markdown bullet lists should: (1) have a blank line before and after the list; (2) start each list item at the beginning of the line (no leading white-space) The markdown processor in Freedom Studio enforces these standards and does not render correctly otherwise. --- bsp/sifive-hifive1/README.md | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) (limited to 'bsp/sifive-hifive1') diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md index 1cc077e..faca2eb 100644 --- a/bsp/sifive-hifive1/README.md +++ b/bsp/sifive-hifive1/README.md @@ -1,12 +1,13 @@ HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV32IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 8 regions - - 16 local interrupts signal that can be connected to off core complex devices - - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - - GPIO memory with 16 interrupt lines - - SPI memory with 1 intterupt line - - Serial port with 1 interrupt line - - 1 RGB LEDS + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 intterupt line +- Serial port with 1 interrupt line +- 1 RGB LEDS -- cgit v1.2.3 From cbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Wed, 27 Feb 2019 15:46:57 -0800 Subject: Spellcheck correction readme for bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/sifive-hifive1/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'bsp/sifive-hifive1') diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md index faca2eb..6311207 100644 --- a/bsp/sifive-hifive1/README.md +++ b/bsp/sifive-hifive1/README.md @@ -1,13 +1,13 @@ HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. -his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: +This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports: - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines -- SPI memory with 1 intterupt line +- SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 1 RGB LEDS -- cgit v1.2.3