From 0af076bd25030fe95336a6314809b0552891225f Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Fri, 15 Feb 2019 15:47:35 -0800 Subject: Add RISCV_CMODEL to settings.mk Signed-off-by: Nathaniel Graff --- bsp/coreip-e24-arty/settings.mk | 1 + bsp/coreip-e31-arty/settings.mk | 1 + bsp/coreip-e31/settings.mk | 1 + bsp/coreip-s51-arty/settings.mk | 1 + bsp/coreip-s51/settings.mk | 1 + bsp/freedom-e310-arty/settings.mk | 1 + bsp/sifive-hifive1/settings.mk | 1 + 7 files changed, 7 insertions(+) (limited to 'bsp') diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk index 31143b5..829d3e8 100644 --- a/bsp/coreip-e24-arty/settings.mk +++ b/bsp/coreip-e24-arty/settings.mk @@ -1,2 +1,3 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk index 31143b5..829d3e8 100644 --- a/bsp/coreip-e31-arty/settings.mk +++ b/bsp/coreip-e31-arty/settings.mk @@ -1,2 +1,3 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow diff --git a/bsp/coreip-e31/settings.mk b/bsp/coreip-e31/settings.mk index 0c818ec..32bb84d 100644 --- a/bsp/coreip-e31/settings.mk +++ b/bsp/coreip-e31/settings.mk @@ -2,4 +2,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk index 1627f4b..3f994a3 100644 --- a/bsp/coreip-s51-arty/settings.mk +++ b/bsp/coreip-s51-arty/settings.mk @@ -1,2 +1,3 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 +RISCV_CMODEL=medany diff --git a/bsp/coreip-s51/settings.mk b/bsp/coreip-s51/settings.mk index 553417e..a3cd0bb 100644 --- a/bsp/coreip-s51/settings.mk +++ b/bsp/coreip-s51/settings.mk @@ -1,3 +1,4 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 COREIP_MEM_WIDTH=64 +RISCV_CMODEL=medany diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk index eacecc3..b7a7782 100644 --- a/bsp/freedom-e310-arty/settings.mk +++ b/bsp/freedom-e310-arty/settings.mk @@ -2,3 +2,4 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODE=medlow diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk index b9424bc..fd73559 100644 --- a/bsp/sifive-hifive1/settings.mk +++ b/bsp/sifive-hifive1/settings.mk @@ -1,2 +1,3 @@ RISCV_ARCH = rv32imac RISCV_ABI = ilp32 +RISCV_CMODEL = medlow -- cgit v1.2.1-18-gbd029