From 43b6767541e6b20d7f7c2aef39b3a4748e53b6e4 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Fri, 1 Mar 2019 15:28:49 -0800 Subject: Update CoreIPs E20, E21, E31 and E24 for 19.2 rel --- bsp/coreip-e20/design.dts | 32 ++--- bsp/coreip-e20/metal.h | 11 -- bsp/coreip-e21/README.md | 2 +- bsp/coreip-e21/design.dts | 4 +- bsp/coreip-e24/README.md | 8 ++ bsp/coreip-e24/design.dts | 97 ++++++++++++++ bsp/coreip-e24/metal.h | 310 +++++++++++++++++++++++++++++++++++++++++++++ bsp/coreip-e24/metal.lds | 223 ++++++++++++++++++++++++++++++++ bsp/coreip-e24/settings.mk | 5 + bsp/coreip-e31/design.dts | 39 +++--- 10 files changed, 677 insertions(+), 54 deletions(-) create mode 100644 bsp/coreip-e24/README.md create mode 100644 bsp/coreip-e24/design.dts create mode 100644 bsp/coreip-e24/metal.h create mode 100644 bsp/coreip-e24/metal.lds create mode 100644 bsp/coreip-e24/settings.mk (limited to 'bsp') diff --git a/bsp/coreip-e20/design.dts b/bsp/coreip-e20/design.dts index f3c25a5..d57c342 100644 --- a/bsp/coreip-e20/design.dts +++ b/bsp/coreip-e20/design.dts @@ -5,10 +5,10 @@ #size-cells = <1>; compatible = "SiFive,FE200G-dev", "fe200-dev", "sifive-dev"; model = "SiFive,FE200G"; - L11: cpus { + L10: cpus { #address-cells = <1>; #size-cells = <0>; - L4: cpu@0 { + L3: cpu@0 { clock-frequency = <0>; compatible = "sifive,caboose0", "riscv"; device_type = "cpu"; @@ -17,55 +17,47 @@ status = "okay"; timebase-frequency = <1000000>; hardware-exec-breakpoint-count = <4>; - L3: interrupt-controller { + L2: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; }; }; }; - L10: soc { + L9: soc { #address-cells = <1>; #size-cells = <1>; compatible = "SiFive,FE200G-soc", "fe200-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; - L8: ahb-sys-port@20000000 { + L7: ahb-sys-port@20000000 { #address-cells = <1>; #size-cells = <1>; compatible = "sifive,ahb-sys-port", "sifive,ahb-port", "sifive,sys-port", "simple-bus"; ranges = <0x20000000 0x20000000 0x20000000>; }; - L2: debug-controller@0 { + L1: debug-controller@0 { compatible = "sifive,debug-013", "riscv,debug-013"; - interrupts-extended = <&L3 65535>; + interrupts-extended = <&L2 65535>; reg = <0x0 0x1000>; reg-names = "control"; }; - L0: error-device@3000 { - compatible = "sifive,error0"; - reg = <0x3000 0x1000>; - }; - L1: interrupt-controller@2000000 { + L0: interrupt-controller@2000000 { #interrupt-cells = <1>; compatible = "sifive,clic0"; interrupt-controller; - interrupts-extended = <&L3 3 &L3 7 &L3 11>; + interrupts-extended = <&L2 3 &L2 7 &L2 11>; reg = <0x2000000 0x1000000>; reg-names = "control"; sifive,numints = <48>; sifive,numlevels = <16>; sifive,numintbits = <2>; }; - L7: local-external-interrupts-0 { + L6: local-external-interrupts-0 { compatible = "sifive,local-external-interrupts0"; - interrupt-parent = <&L1>; + interrupt-parent = <&L0>; interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; }; - L5: teststatus@4000 { + L4: teststatus@4000 { compatible = "sifive,test0"; reg = <0x4000 0x1000>; reg-names = "control"; diff --git a/bsp/coreip-e20/metal.h b/bsp/coreip-e20/metal.h index e132a8e..5693e03 100644 --- a/bsp/coreip-e20/metal.h +++ b/bsp/coreip-e20/metal.h @@ -49,9 +49,6 @@ struct __metal_driver_cpu __metal_dt_cpu_0; asm (".weak __metal_dt_interrupt_controller"); struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; -asm (".weak __metal_dt_pmp_0"); -struct metal_pmp __metal_dt_pmp_0; - /* From interrupt_controller@2000000 */ asm (".weak __metal_dt_interrupt_controller_2000000"); struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; @@ -81,11 +78,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { .interrupt_controller = 1, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = 8UL, -}; - /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .vtable = &__metal_driver_vtable_sifive_clic0, @@ -171,9 +163,6 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) - /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e21/README.md b/bsp/coreip-e21/README.md index a2f1a61..6b74a44 100644 --- a/bsp/coreip-e21/README.md +++ b/bsp/coreip-e21/README.md @@ -4,4 +4,4 @@ This core target is suitable with Verilog RTL for verification and running appli - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 4 regions +- Physical Memory Protection with 4 regions diff --git a/bsp/coreip-e21/design.dts b/bsp/coreip-e21/design.dts index 4cd74ef..9e846c0 100644 --- a/bsp/coreip-e21/design.dts +++ b/bsp/coreip-e21/design.dts @@ -71,12 +71,12 @@ interrupt-parent = <&L1>; interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126>; }; - L6: sys-sram@80000000 { + L6: sys-sram-0@80000000 { compatible = "sifive,sram0"; reg = <0x80000000 0x8000>; reg-names = "mem"; }; - L7: sys-sram@80008000 { + L7: sys-sram-1@80008000 { compatible = "sifive,sram0"; reg = <0x80008000 0x8000>; reg-names = "mem"; diff --git a/bsp/coreip-e24/README.md b/bsp/coreip-e24/README.md new file mode 100644 index 0000000..1996262 --- /dev/null +++ b/bsp/coreip-e24/README.md @@ -0,0 +1,8 @@ +The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA’s F standard extension. The E24’s efficiency, coupled with hardware floating-point capabilities, make it exceptional at motor control, sensor fusion, and IoT applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions + diff --git a/bsp/coreip-e24/design.dts b/bsp/coreip-e24/design.dts new file mode 100644 index 0000000..da1b792 --- /dev/null +++ b/bsp/coreip-e24/design.dts @@ -0,0 +1,97 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FE240G-dev", "fe240-dev", "sifive-dev"; + model = "SiFive,FE240G"; + L14: cpus { + #address-cells = <1>; + #size-cells = <0>; + L4: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,caboose0", "riscv"; + device_type = "cpu"; + reg = <0x0>; + riscv,isa = "rv32imafc"; + status = "okay"; + timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; + L3: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L13: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FE240G-soc", "fe240-soc", "sifive-soc", "simple-bus"; + ranges; + pmp: pmp@0 { + compatible = "riscv,pmp"; + regions = <8>; + }; + L11: ahb-periph-port@20000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sifive,ahb-periph-port", "sifive,ahb-port", "sifive,periph-port", "simple-bus"; + ranges = <0x20000000 0x20000000 0x20000000>; + }; + L10: ahb-sys-port@40000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "sifive,ahb-sys-port", "sifive,ahb-port", "sifive,sys-port", "simple-bus"; + ranges = <0x40000000 0x40000000 0x20000000>; + }; + L2: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L3 65535>; + reg = <0x0 0x1000>; + reg-names = "control"; + }; + L0: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + reg-names = "mem"; + }; + L1: interrupt-controller@2000000 { + #interrupt-cells = <1>; + compatible = "sifive,clic0"; + interrupt-controller; + interrupts-extended = <&L3 3 &L3 7 &L3 11>; + reg = <0x2000000 0x1000000>; + reg-names = "control"; + sifive,numints = <143>; + sifive,numlevels = <16>; + sifive,numintbits = <4>; + }; + L9: local-external-interrupts-0 { + compatible = "sifive,local-external-interrupts0"; + interrupt-parent = <&L1>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126>; + }; + L6: sys-sram-0@80000000 { + compatible = "sifive,sram0"; + reg = <0x80000000 0x8000>; + reg-names = "mem"; + }; + L7: sys-sram-1@80008000 { + compatible = "sifive,sram0"; + reg = <0x80008000 0x8000>; + reg-names = "mem"; + }; + L5: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x4000 0x1000>; + reg-names = "control"; + }; + test_memory: testram@20000000 { + compatible = "sifive,testram0"; + reg = <0x20000000 0x8000000>; + reg-names = "mem"; + word-size-bytes = <4>; + }; + }; +}; diff --git a/bsp/coreip-e24/metal.h b/bsp/coreip-e24/metal.h new file mode 100644 index 0000000..1d23799 --- /dev/null +++ b/bsp/coreip-e24/metal.h @@ -0,0 +1,310 @@ +#ifndef ASSEMBLY + +#ifndef COREIP_E24__METAL_H +#define COREIP_E24__METAL_H + +#ifdef __METAL_MACHINE_MACROS + +#define __METAL_CLIC_SUBINTERRUPTS 143 + +#ifndef __METAL_CLIC_SUBINTERRUPTS +#define __METAL_CLIC_SUBINTERRUPTS 0 +#endif + +#else /* ! __METAL_MACHINE_MACROS */ + +#define METAL_MAX_CLINT_INTERRUPTS 0 + +#define METAL_MAX_PLIC_INTERRUPTS 0 + +#define __METAL_INTERRUPT_CONTROLLER_2000000_INTERRUPTS 3 + +#define __METAL_CLIC_SUBINTERRUPTS 143 + +#define METAL_MAX_CLIC_INTERRUPTS 3 + +#define __METAL_LOCAL_EXTERNAL_INTERRUPTS_0_INTERRUPTS 127 + +#define METAL_MAX_LOCAL_EXT_INTERRUPTS 127 + +#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 0 + +#define METAL_MAX_GPIO_INTERRUPTS 0 + +#define METAL_MAX_UART_INTERRUPTS 0 + + +#include +#include +#include +#include +#include +#include + +/* From cpu@0 */ +asm (".weak __metal_dt_cpu_0"); +struct __metal_driver_cpu __metal_dt_cpu_0; + +/* From interrupt_controller */ +asm (".weak __metal_dt_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; + +asm (".weak __metal_dt_pmp_0"); +struct metal_pmp __metal_dt_pmp_0; + +/* From interrupt_controller@2000000 */ +asm (".weak __metal_dt_interrupt_controller_2000000"); +struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; + +/* From local_external_interrupts_0 */ +asm (".weak __metal_dt_local_external_interrupts_0"); +struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; + +/* From teststatus@4000 */ +asm (".weak __metal_dt_teststatus_4000"); +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; + + +/* From cpu@0 */ +struct __metal_driver_cpu __metal_dt_cpu_0 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_interrupt_controller.controller, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From pmp@0 */ +struct metal_pmp __metal_dt_pmp_0 = { + .num_regions = 8UL, +}; + +/* From interrupt_controller@2000000 */ +struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { + .vtable = &__metal_driver_vtable_sifive_clic0, + .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, + .control_base = 33554432UL, + .control_size = 16777216UL, + .init_done = 0, + .num_interrupts = METAL_MAX_CLIC_INTERRUPTS, + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_lines[0] = 3, + .interrupt_lines[1] = 7, + .interrupt_lines[2] = 11, + .num_subinterrupts = 143UL, + .num_intbits = 4UL, + .max_levels = 16UL, + .interrupt_controller = 1, +}; + +/* From local_external_interrupts_0 */ +struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { + .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, + .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, + .init_done = 0, +/* From interrupt_controller@2000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller, + .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, + .interrupt_lines[0] = 0, + .interrupt_lines[1] = 1, + .interrupt_lines[2] = 2, + .interrupt_lines[3] = 3, + .interrupt_lines[4] = 4, + .interrupt_lines[5] = 5, + .interrupt_lines[6] = 6, + .interrupt_lines[7] = 7, + .interrupt_lines[8] = 8, + .interrupt_lines[9] = 9, + .interrupt_lines[10] = 10, + .interrupt_lines[11] = 11, + .interrupt_lines[12] = 12, + .interrupt_lines[13] = 13, + .interrupt_lines[14] = 14, + .interrupt_lines[15] = 15, + .interrupt_lines[16] = 16, + .interrupt_lines[17] = 17, + .interrupt_lines[18] = 18, + .interrupt_lines[19] = 19, + .interrupt_lines[20] = 20, + .interrupt_lines[21] = 21, + .interrupt_lines[22] = 22, + .interrupt_lines[23] = 23, + .interrupt_lines[24] = 24, + .interrupt_lines[25] = 25, + .interrupt_lines[26] = 26, + .interrupt_lines[27] = 27, + .interrupt_lines[28] = 28, + .interrupt_lines[29] = 29, + .interrupt_lines[30] = 30, + .interrupt_lines[31] = 31, + .interrupt_lines[32] = 32, + .interrupt_lines[33] = 33, + .interrupt_lines[34] = 34, + .interrupt_lines[35] = 35, + .interrupt_lines[36] = 36, + .interrupt_lines[37] = 37, + .interrupt_lines[38] = 38, + .interrupt_lines[39] = 39, + .interrupt_lines[40] = 40, + .interrupt_lines[41] = 41, + .interrupt_lines[42] = 42, + .interrupt_lines[43] = 43, + .interrupt_lines[44] = 44, + .interrupt_lines[45] = 45, + .interrupt_lines[46] = 46, + .interrupt_lines[47] = 47, + .interrupt_lines[48] = 48, + .interrupt_lines[49] = 49, + .interrupt_lines[50] = 50, + .interrupt_lines[51] = 51, + .interrupt_lines[52] = 52, + .interrupt_lines[53] = 53, + .interrupt_lines[54] = 54, + .interrupt_lines[55] = 55, + .interrupt_lines[56] = 56, + .interrupt_lines[57] = 57, + .interrupt_lines[58] = 58, + .interrupt_lines[59] = 59, + .interrupt_lines[60] = 60, + .interrupt_lines[61] = 61, + .interrupt_lines[62] = 62, + .interrupt_lines[63] = 63, + .interrupt_lines[64] = 64, + .interrupt_lines[65] = 65, + .interrupt_lines[66] = 66, + .interrupt_lines[67] = 67, + .interrupt_lines[68] = 68, + .interrupt_lines[69] = 69, + .interrupt_lines[70] = 70, + .interrupt_lines[71] = 71, + .interrupt_lines[72] = 72, + .interrupt_lines[73] = 73, + .interrupt_lines[74] = 74, + .interrupt_lines[75] = 75, + .interrupt_lines[76] = 76, + .interrupt_lines[77] = 77, + .interrupt_lines[78] = 78, + .interrupt_lines[79] = 79, + .interrupt_lines[80] = 80, + .interrupt_lines[81] = 81, + .interrupt_lines[82] = 82, + .interrupt_lines[83] = 83, + .interrupt_lines[84] = 84, + .interrupt_lines[85] = 85, + .interrupt_lines[86] = 86, + .interrupt_lines[87] = 87, + .interrupt_lines[88] = 88, + .interrupt_lines[89] = 89, + .interrupt_lines[90] = 90, + .interrupt_lines[91] = 91, + .interrupt_lines[92] = 92, + .interrupt_lines[93] = 93, + .interrupt_lines[94] = 94, + .interrupt_lines[95] = 95, + .interrupt_lines[96] = 96, + .interrupt_lines[97] = 97, + .interrupt_lines[98] = 98, + .interrupt_lines[99] = 99, + .interrupt_lines[100] = 100, + .interrupt_lines[101] = 101, + .interrupt_lines[102] = 102, + .interrupt_lines[103] = 103, + .interrupt_lines[104] = 104, + .interrupt_lines[105] = 105, + .interrupt_lines[106] = 106, + .interrupt_lines[107] = 107, + .interrupt_lines[108] = 108, + .interrupt_lines[109] = 109, + .interrupt_lines[110] = 110, + .interrupt_lines[111] = 111, + .interrupt_lines[112] = 112, + .interrupt_lines[113] = 113, + .interrupt_lines[114] = 114, + .interrupt_lines[115] = 115, + .interrupt_lines[116] = 116, + .interrupt_lines[117] = 117, + .interrupt_lines[118] = 118, + .interrupt_lines[119] = 119, + .interrupt_lines[120] = 120, + .interrupt_lines[121] = 121, + .interrupt_lines[122] = 122, + .interrupt_lines[123] = 123, + .interrupt_lines[124] = 124, + .interrupt_lines[125] = 125, + .interrupt_lines[126] = 126, +}; + +/* From teststatus@4000 */ +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { + .vtable = &__metal_driver_vtable_sifive_test0, + .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown, + .base = 16384UL, + .size = 4096UL, +}; + + +/* From cpu@0 */ +#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) + +#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) + +#define __METAL_DT_MAX_HARTS 1 + +asm (".weak __metal_cpu_table"); +struct __metal_driver_cpu *__metal_cpu_table[] = { + &__metal_dt_cpu_0}; + +/* From interrupt_controller */ +#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) + +/* From pmp@0 */ +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) + +/* From interrupt_controller@2000000 */ +#define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_2000000_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) + +/* From local_external_interrupts_0 */ +#define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) + +#define __METAL_DT_LOCAL_EXTERNAL_INTERRUPTS_0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) + +#define __METAL_DT_MAX_BUTTONS 0 + +asm (".weak __metal_button_table"); +struct __metal_driver_sifive_gpio_button *__metal_button_table[] = { + NULL }; +#define __METAL_DT_MAX_LEDS 0 + +asm (".weak __metal_led_table"); +struct __metal_driver_sifive_gpio_led *__metal_led_table[] = { + NULL }; +#define __METAL_DT_MAX_SWITCHES 0 + +asm (".weak __metal_switch_table"); +struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = { + NULL }; +#define __METAL_DT_MAX_SPIS 0 + +asm (".weak __metal_spi_table"); +struct __metal_driver_sifive_spi0 *__metal_spi_table[] = { + NULL }; +/* From teststatus@4000 */ +#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_teststatus_4000.shutdown) + +#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown) + + +#endif /* ! __METAL_MACHINE_MACROS */ +#endif /* COREIP_E24__METAL_H*/ +#endif /* ! ASSEMBLY */ diff --git a/bsp/coreip-e24/metal.lds b/bsp/coreip-e24/metal.lds new file mode 100644 index 0000000..d98efc5 --- /dev/null +++ b/bsp/coreip-e24/metal.lds @@ -0,0 +1,223 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 0x8000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_LOAD; + itim PT_LOAD; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + } >ram AT>ram :ram + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.itim .itim.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >ram AT>ram :ram + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >ram AT>ram :ram_init + + + .itim : + { + } >ram AT>ram :ram_init + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >ram AT>ram :ram + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>ram :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-e24/settings.mk b/bsp/coreip-e24/settings.mk new file mode 100644 index 0000000..0c818ec --- /dev/null +++ b/bsp/coreip-e24/settings.mk @@ -0,0 +1,5 @@ +#write_config_file + +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 +COREIP_MEM_WIDTH=32 diff --git a/bsp/coreip-e31/design.dts b/bsp/coreip-e31/design.dts index c589362..7c527ec 100644 --- a/bsp/coreip-e31/design.dts +++ b/bsp/coreip-e31/design.dts @@ -8,21 +8,21 @@ L15: cpus { #address-cells = <1>; #size-cells = <0>; - L6: cpu@0 { + L7: cpu@0 { clock-frequency = <0>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>; i-cache-sets = <128>; i-cache-size = <16384>; - reg = <0>; + reg = <0x0>; riscv,isa = "rv32imac"; - sifive,dtim = <&L5>; - sifive,itim = <&L4>; + sifive,dtim = <&L6>; + sifive,itim = <&L5>; status = "okay"; timebase-frequency = <1000000>; hardware-exec-breakpoint-count = <4>; - L3: interrupt-controller { + L4: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; interrupt-controller; @@ -41,63 +41,62 @@ L12: ahb-periph-port@20000000 { #address-cells = <1>; #size-cells = <1>; - compatible = "simple-bus"; + compatible = "sifive,ahb-periph-port", "sifive,ahb-port", "sifive,periph-port", "simple-bus"; ranges = <0x20000000 0x20000000 0x20000000>; }; L11: ahb-sys-port@40000000 { #address-cells = <1>; #size-cells = <1>; - compatible = "simple-bus"; + compatible = "sifive,ahb-sys-port", "sifive,ahb-port", "sifive,sys-port", "simple-bus"; ranges = <0x40000000 0x40000000 0x20000000>; }; - L1: clint@2000000 { + L2: clint@2000000 { compatible = "riscv,clint0"; - interrupts-extended = <&L3 3 &L3 7>; + interrupts-extended = <&L4 3 &L4 7>; reg = <0x2000000 0x10000>; reg-names = "control"; }; - L2: debug-controller@0 { + L3: debug-controller@0 { compatible = "sifive,debug-013", "riscv,debug-013"; - interrupts-extended = <&L3 65535>; + interrupts-extended = <&L4 65535>; reg = <0x0 0x1000>; reg-names = "control"; }; - L5: dtim@80000000 { + L6: dtim@80000000 { compatible = "sifive,dtim0"; reg = <0x80000000 0x10000>; reg-names = "mem"; }; - L8: error-device@3000 { + L0: error-device@3000 { compatible = "sifive,error0"; reg = <0x3000 0x1000>; - reg-names = "mem"; }; L9: global-external-interrupts { compatible = "sifive,global-external-interrupts0"; - interrupt-parent = <&L0>; + interrupt-parent = <&L1>; interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>; }; - L0: interrupt-controller@c000000 { + L1: interrupt-controller@c000000 { #interrupt-cells = <1>; compatible = "riscv,plic0"; interrupt-controller; - interrupts-extended = <&L3 11>; + interrupts-extended = <&L4 11>; reg = <0xc000000 0x4000000>; reg-names = "control"; riscv,max-priority = <7>; riscv,ndev = <127>; }; - L4: itim@8000000 { + L5: itim@8000000 { compatible = "sifive,itim0"; reg = <0x8000000 0x4000>; reg-names = "mem"; }; L10: local-external-interrupts-0 { compatible = "sifive,local-external-interrupts0"; - interrupt-parent = <&L3>; + interrupt-parent = <&L4>; interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; }; - L7: teststatus@4000 { + L8: teststatus@4000 { compatible = "sifive,test0"; reg = <0x4000 0x1000>; reg-names = "control"; -- cgit v1.2.1-18-gbd029