From 5016845c243e08c21e21c623c33c744da5689f6f Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Mon, 11 Feb 2019 17:03:33 -0800 Subject: Update BSPs for hw-exec-breakpoint --- bsp/coreip-e24-arty/design.dts | 1 + bsp/coreip-e31-arty/design.dts | 1 + bsp/coreip-e31/design.dts | 1 + bsp/coreip-s51-arty/design.dts | 1 + bsp/coreip-s51/design.dts | 1 + bsp/freedom-e310-arty/design.dts | 1 + bsp/sifive-hifive1/design.dts | 1 + 7 files changed, 7 insertions(+) (limited to 'bsp') diff --git a/bsp/coreip-e24-arty/design.dts b/bsp/coreip-e24-arty/design.dts index 780cc7b..9699fae 100644 --- a/bsp/coreip-e24-arty/design.dts +++ b/bsp/coreip-e24-arty/design.dts @@ -23,6 +23,7 @@ riscv,isa = "rv32imafc"; status = "okay"; timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; L3: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts index c69740e..03e100b 100644 --- a/bsp/coreip-e31-arty/design.dts +++ b/bsp/coreip-e31-arty/design.dts @@ -28,6 +28,7 @@ sifive,itim = <&L4>; status = "okay"; timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; L3: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; diff --git a/bsp/coreip-e31/design.dts b/bsp/coreip-e31/design.dts index f7e9868..c589362 100644 --- a/bsp/coreip-e31/design.dts +++ b/bsp/coreip-e31/design.dts @@ -21,6 +21,7 @@ sifive,itim = <&L4>; status = "okay"; timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; L3: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts index 6c7379d..0378ec3 100644 --- a/bsp/coreip-s51-arty/design.dts +++ b/bsp/coreip-s51-arty/design.dts @@ -28,6 +28,7 @@ sifive,itim = <&L4>; status = "okay"; timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; L3: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; diff --git a/bsp/coreip-s51/design.dts b/bsp/coreip-s51/design.dts index a1cb9fc..9cf3a29 100644 --- a/bsp/coreip-s51/design.dts +++ b/bsp/coreip-s51/design.dts @@ -21,6 +21,7 @@ sifive,itim = <&L4>; status = "okay"; timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; L3: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; diff --git a/bsp/freedom-e310-arty/design.dts b/bsp/freedom-e310-arty/design.dts index 74da572..0935af9 100644 --- a/bsp/freedom-e310-arty/design.dts +++ b/bsp/freedom-e310-arty/design.dts @@ -29,6 +29,7 @@ sifive,itim = <&itim>; status = "okay"; timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; hlic: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts index abccd6c..ff95ae0 100644 --- a/bsp/sifive-hifive1/design.dts +++ b/bsp/sifive-hifive1/design.dts @@ -28,6 +28,7 @@ sifive,dtim = <&dtim>; status = "okay"; timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; hlic: interrupt-controller { #interrupt-cells = <1>; compatible = "riscv,cpu-intc"; -- cgit v1.2.1-18-gbd029