From 72efc798890672897fd54332d29afb0956a1c73e Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 14 Mar 2019 13:42:04 -0700 Subject: Fix typos and formatting in settings.mk Signed-off-by: Nathaniel Graff --- bsp/coreip-e20-arty/settings.mk | 1 + bsp/coreip-e20-rtl/settings.mk | 3 +-- bsp/coreip-e21-arty/settings.mk | 1 + bsp/coreip-e21-rtl/settings.mk | 3 +-- bsp/coreip-e24-rtl/settings.mk | 3 +-- bsp/coreip-e31-rtl/settings.mk | 3 +-- bsp/coreip-e34-rtl/settings.mk | 3 +-- bsp/coreip-e76-arty/settings.mk | 1 + bsp/coreip-e76-rtl/settings.mk | 3 +-- bsp/coreip-s51-rtl/settings.mk | 3 ++- bsp/coreip-s54-arty/settings.mk | 2 +- bsp/coreip-s54-rtl/settings.mk | 3 ++- bsp/coreip-s76-arty/settings.mk | 1 + bsp/coreip-s76-rtl/settings.mk | 1 + bsp/freedom-e310-arty/settings.mk | 4 +--- bsp/sifive-hifive1-revb/settings.mk | 9 +++++---- bsp/sifive-hifive1/settings.mk | 6 +++--- 17 files changed, 25 insertions(+), 25 deletions(-) (limited to 'bsp') diff --git a/bsp/coreip-e20-arty/settings.mk b/bsp/coreip-e20-arty/settings.mk index 9d61abe..0b9c2cb 100644 --- a/bsp/coreip-e20-arty/settings.mk +++ b/bsp/coreip-e20-arty/settings.mk @@ -1,4 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e20-rtl/settings.mk b/bsp/coreip-e20-rtl/settings.mk index 19a7b2b..699498e 100644 --- a/bsp/coreip-e20-rtl/settings.mk +++ b/bsp/coreip-e20-rtl/settings.mk @@ -1,8 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imc RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk index 9d61abe..0b9c2cb 100644 --- a/bsp/coreip-e21-arty/settings.mk +++ b/bsp/coreip-e21-arty/settings.mk @@ -1,4 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e21-rtl/settings.mk b/bsp/coreip-e21-rtl/settings.mk index c3f98c4..f60f250 100644 --- a/bsp/coreip-e21-rtl/settings.mk +++ b/bsp/coreip-e21-rtl/settings.mk @@ -1,8 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl diff --git a/bsp/coreip-e24-rtl/settings.mk b/bsp/coreip-e24-rtl/settings.mk index c3f98c4..f60f250 100644 --- a/bsp/coreip-e24-rtl/settings.mk +++ b/bsp/coreip-e24-rtl/settings.mk @@ -1,8 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk index c3f98c4..f60f250 100644 --- a/bsp/coreip-e31-rtl/settings.mk +++ b/bsp/coreip-e31-rtl/settings.mk @@ -1,8 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl diff --git a/bsp/coreip-e34-rtl/settings.mk b/bsp/coreip-e34-rtl/settings.mk index c3f98c4..f60f250 100644 --- a/bsp/coreip-e34-rtl/settings.mk +++ b/bsp/coreip-e34-rtl/settings.mk @@ -1,8 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=32 TARGET_TAGS=rtl diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk index 9d61abe..0b9c2cb 100644 --- a/bsp/coreip-e76-arty/settings.mk +++ b/bsp/coreip-e76-arty/settings.mk @@ -1,4 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 +RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk index 4a9e97f..dd09d48 100644 --- a/bsp/coreip-e76-rtl/settings.mk +++ b/bsp/coreip-e76-rtl/settings.mk @@ -1,8 +1,7 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl diff --git a/bsp/coreip-s51-rtl/settings.mk b/bsp/coreip-s51-rtl/settings.mk index 78ef056..4d48fc1 100644 --- a/bsp/coreip-s51-rtl/settings.mk +++ b/bsp/coreip-s51-rtl/settings.mk @@ -1,6 +1,7 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 -COREIP_MEM_WIDTH=64 RISCV_CMODEL=medany +COREIP_MEM_WIDTH=64 + TARGET_TAGS=rtl diff --git a/bsp/coreip-s54-arty/settings.mk b/bsp/coreip-s54-arty/settings.mk index 684f76d..2832d7c 100644 --- a/bsp/coreip-s54-arty/settings.mk +++ b/bsp/coreip-s54-arty/settings.mk @@ -1,5 +1,5 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 -iRISCV_CMODEL=medany +RISCV_CMODEL=medany TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-s54-rtl/settings.mk b/bsp/coreip-s54-rtl/settings.mk index e6b6330..4d48fc1 100644 --- a/bsp/coreip-s54-rtl/settings.mk +++ b/bsp/coreip-s54-rtl/settings.mk @@ -1,6 +1,7 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 -RISCV_CMODE=medany +RISCV_CMODEL=medany + COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk index 3c7d718..2832d7c 100644 --- a/bsp/coreip-s76-arty/settings.mk +++ b/bsp/coreip-s76-arty/settings.mk @@ -1,4 +1,5 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 +RISCV_CMODEL=medany TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-s76-rtl/settings.mk b/bsp/coreip-s76-rtl/settings.mk index 4aeb6b5..4d48fc1 100644 --- a/bsp/coreip-s76-rtl/settings.mk +++ b/bsp/coreip-s76-rtl/settings.mk @@ -1,6 +1,7 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 RISCV_CMODEL=medany + COREIP_MEM_WIDTH=64 TARGET_TAGS=rtl diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk index a2774d2..0b9c2cb 100644 --- a/bsp/freedom-e310-arty/settings.mk +++ b/bsp/freedom-e310-arty/settings.mk @@ -1,7 +1,5 @@ -#write_config_file - RISCV_ARCH=rv32imac RISCV_ABI=ilp32 -RISCV_CMODE=medlow +RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk index d0c3628..fc5f172 100644 --- a/bsp/sifive-hifive1-revb/settings.mk +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -1,6 +1,7 @@ -RISCV_ARCH = rv32imac -RISCV_ABI = ilp32 -RISCV_CMODEL = medlow -SEGGER_JLINK_OB = 1 +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 +RISCV_CMODEL=medlow + +SEGGER_JLINK_OB=1 TARGET_TAGS=board jlink diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk index ba1ed20..d863a6d 100644 --- a/bsp/sifive-hifive1/settings.mk +++ b/bsp/sifive-hifive1/settings.mk @@ -1,5 +1,5 @@ -RISCV_ARCH = rv32imac -RISCV_ABI = ilp32 -RISCV_CMODEL = medlow +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 +RISCV_CMODEL=medlow TARGET_TAGS=board openocd -- cgit v1.2.1-18-gbd029