From 77954fc86e0236d90a8b171200b77198baa362ec Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 14 Mar 2019 13:36:25 -0700 Subject: Create TARGET_TAGS Signed-off-by: Nathaniel Graff --- bsp/coreip-e20-arty/settings.mk | 2 ++ bsp/coreip-e20-rtl/settings.mk | 2 ++ bsp/coreip-e21-arty/settings.mk | 2 ++ bsp/coreip-e21-rtl/settings.mk | 2 ++ bsp/coreip-e24-arty/settings.mk | 2 ++ bsp/coreip-e24-rtl/settings.mk | 2 ++ bsp/coreip-e31-arty/settings.mk | 2 ++ bsp/coreip-e31-rtl/settings.mk | 2 ++ bsp/coreip-e34-arty/settings.mk | 2 ++ bsp/coreip-e34-rtl/settings.mk | 2 ++ bsp/coreip-e76-arty/settings.mk | 2 ++ bsp/coreip-e76-rtl/settings.mk | 2 ++ bsp/coreip-s51-arty/settings.mk | 2 ++ bsp/coreip-s51-rtl/settings.mk | 2 ++ bsp/coreip-s54-arty/settings.mk | 2 ++ bsp/coreip-s54-rtl/settings.mk | 2 ++ bsp/coreip-s76-arty/settings.mk | 2 ++ bsp/coreip-s76-rtl/settings.mk | 2 ++ bsp/freedom-e310-arty/settings.mk | 2 ++ bsp/sifive-hifive1-revb/settings.mk | 2 ++ bsp/sifive-hifive1/settings.mk | 2 ++ 21 files changed, 42 insertions(+) (limited to 'bsp') diff --git a/bsp/coreip-e20-arty/settings.mk b/bsp/coreip-e20-arty/settings.mk index 31143b5..9d61abe 100644 --- a/bsp/coreip-e20-arty/settings.mk +++ b/bsp/coreip-e20-arty/settings.mk @@ -1,2 +1,4 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e20-rtl/settings.mk b/bsp/coreip-e20-rtl/settings.mk index 1ac4d9f..19a7b2b 100644 --- a/bsp/coreip-e20-rtl/settings.mk +++ b/bsp/coreip-e20-rtl/settings.mk @@ -4,3 +4,5 @@ RISCV_ARCH=rv32imc RISCV_ABI=ilp32 RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk index 31143b5..9d61abe 100644 --- a/bsp/coreip-e21-arty/settings.mk +++ b/bsp/coreip-e21-arty/settings.mk @@ -1,2 +1,4 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e21-rtl/settings.mk b/bsp/coreip-e21-rtl/settings.mk index 32bb84d..c3f98c4 100644 --- a/bsp/coreip-e21-rtl/settings.mk +++ b/bsp/coreip-e21-rtl/settings.mk @@ -4,3 +4,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk index 829d3e8..0b9c2cb 100644 --- a/bsp/coreip-e24-arty/settings.mk +++ b/bsp/coreip-e24-arty/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e24-rtl/settings.mk b/bsp/coreip-e24-rtl/settings.mk index 32bb84d..c3f98c4 100644 --- a/bsp/coreip-e24-rtl/settings.mk +++ b/bsp/coreip-e24-rtl/settings.mk @@ -4,3 +4,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk index 829d3e8..0b9c2cb 100644 --- a/bsp/coreip-e31-arty/settings.mk +++ b/bsp/coreip-e31-arty/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk index 32bb84d..c3f98c4 100644 --- a/bsp/coreip-e31-rtl/settings.mk +++ b/bsp/coreip-e31-rtl/settings.mk @@ -4,3 +4,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-e34-arty/settings.mk b/bsp/coreip-e34-arty/settings.mk index 829d3e8..0b9c2cb 100644 --- a/bsp/coreip-e34-arty/settings.mk +++ b/bsp/coreip-e34-arty/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e34-rtl/settings.mk b/bsp/coreip-e34-rtl/settings.mk index 32bb84d..c3f98c4 100644 --- a/bsp/coreip-e34-rtl/settings.mk +++ b/bsp/coreip-e34-rtl/settings.mk @@ -4,3 +4,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow COREIP_MEM_WIDTH=32 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk index 31143b5..9d61abe 100644 --- a/bsp/coreip-e76-arty/settings.mk +++ b/bsp/coreip-e76-arty/settings.mk @@ -1,2 +1,4 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk index fd049f4..4a9e97f 100644 --- a/bsp/coreip-e76-rtl/settings.mk +++ b/bsp/coreip-e76-rtl/settings.mk @@ -4,3 +4,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODEL=medlow COREIP_MEM_WIDTH=64 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk index 3f994a3..2832d7c 100644 --- a/bsp/coreip-s51-arty/settings.mk +++ b/bsp/coreip-s51-arty/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 RISCV_CMODEL=medany + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-s51-rtl/settings.mk b/bsp/coreip-s51-rtl/settings.mk index a3cd0bb..78ef056 100644 --- a/bsp/coreip-s51-rtl/settings.mk +++ b/bsp/coreip-s51-rtl/settings.mk @@ -2,3 +2,5 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 COREIP_MEM_WIDTH=64 RISCV_CMODEL=medany + +TARGET_TAGS=rtl diff --git a/bsp/coreip-s54-arty/settings.mk b/bsp/coreip-s54-arty/settings.mk index ab3b474..684f76d 100644 --- a/bsp/coreip-s54-arty/settings.mk +++ b/bsp/coreip-s54-arty/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 iRISCV_CMODEL=medany + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-s54-rtl/settings.mk b/bsp/coreip-s54-rtl/settings.mk index fabb838..e6b6330 100644 --- a/bsp/coreip-s54-rtl/settings.mk +++ b/bsp/coreip-s54-rtl/settings.mk @@ -2,3 +2,5 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 RISCV_CMODE=medany COREIP_MEM_WIDTH=64 + +TARGET_TAGS=rtl diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk index 1627f4b..3c7d718 100644 --- a/bsp/coreip-s76-arty/settings.mk +++ b/bsp/coreip-s76-arty/settings.mk @@ -1,2 +1,4 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 + +TARGET_TAGS=fpga openocd diff --git a/bsp/coreip-s76-rtl/settings.mk b/bsp/coreip-s76-rtl/settings.mk index a7d8dfa..4aeb6b5 100644 --- a/bsp/coreip-s76-rtl/settings.mk +++ b/bsp/coreip-s76-rtl/settings.mk @@ -2,3 +2,5 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 RISCV_CMODEL=medany COREIP_MEM_WIDTH=64 + +TARGET_TAGS=rtl diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk index b7a7782..a2774d2 100644 --- a/bsp/freedom-e310-arty/settings.mk +++ b/bsp/freedom-e310-arty/settings.mk @@ -3,3 +3,5 @@ RISCV_ARCH=rv32imac RISCV_ABI=ilp32 RISCV_CMODE=medlow + +TARGET_TAGS=fpga openocd diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk index 61e2b02..d0c3628 100644 --- a/bsp/sifive-hifive1-revb/settings.mk +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -2,3 +2,5 @@ RISCV_ARCH = rv32imac RISCV_ABI = ilp32 RISCV_CMODEL = medlow SEGGER_JLINK_OB = 1 + +TARGET_TAGS=board jlink diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk index fd73559..ba1ed20 100644 --- a/bsp/sifive-hifive1/settings.mk +++ b/bsp/sifive-hifive1/settings.mk @@ -1,3 +1,5 @@ RISCV_ARCH = rv32imac RISCV_ABI = ilp32 RISCV_CMODEL = medlow + +TARGET_TAGS=board openocd -- cgit v1.2.1-18-gbd029