From c5dd42c68d030a356c85bb8d174296b4f2df615d Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 21 May 2019 10:55:10 -0700 Subject: Update BSPs Signed-off-by: Nathaniel Graff --- bsp/coreip-e20-arty/metal-inline.h | 3 ++- bsp/coreip-e20-arty/metal-platform.h | 2 +- bsp/coreip-e20-arty/metal.default.lds | 2 +- bsp/coreip-e20-arty/metal.h | 12 +++++++++- bsp/coreip-e20-arty/metal.ramrodata.lds | 2 +- bsp/coreip-e20-arty/metal.scratchpad.lds | 2 +- bsp/coreip-e20-arty/settings.mk | 2 +- bsp/coreip-e20-rtl/metal-inline.h | 3 ++- bsp/coreip-e20-rtl/metal-platform.h | 2 +- bsp/coreip-e20-rtl/metal.default.lds | 2 +- bsp/coreip-e20-rtl/metal.h | 12 +++++++++- bsp/coreip-e20-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-e20-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-e20-rtl/settings.mk | 2 +- bsp/coreip-e21-arty/metal-inline.h | 8 ++----- bsp/coreip-e21-arty/metal-platform.h | 7 +----- bsp/coreip-e21-arty/metal.default.lds | 2 +- bsp/coreip-e21-arty/metal.h | 17 ++++++++++---- bsp/coreip-e21-arty/metal.ramrodata.lds | 2 +- bsp/coreip-e21-arty/metal.scratchpad.lds | 2 +- bsp/coreip-e21-arty/settings.mk | 2 +- bsp/coreip-e21-rtl/metal-inline.h | 8 ++----- bsp/coreip-e21-rtl/metal-platform.h | 7 +----- bsp/coreip-e21-rtl/metal.default.lds | 2 +- bsp/coreip-e21-rtl/metal.h | 17 ++++++++++---- bsp/coreip-e21-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-e21-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-e21-rtl/settings.mk | 2 +- bsp/coreip-e24-arty/metal-inline.h | 8 ++----- bsp/coreip-e24-arty/metal-platform.h | 7 +----- bsp/coreip-e24-arty/metal.default.lds | 2 +- bsp/coreip-e24-arty/metal.h | 17 ++++++++++---- bsp/coreip-e24-arty/metal.ramrodata.lds | 2 +- bsp/coreip-e24-arty/metal.scratchpad.lds | 2 +- bsp/coreip-e24-arty/settings.mk | 2 +- bsp/coreip-e24-rtl/metal-inline.h | 8 ++----- bsp/coreip-e24-rtl/metal-platform.h | 7 +----- bsp/coreip-e24-rtl/metal.default.lds | 2 +- bsp/coreip-e24-rtl/metal.h | 17 ++++++++++---- bsp/coreip-e24-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-e24-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-e24-rtl/settings.mk | 2 +- bsp/coreip-e31-arty/metal-inline.h | 8 ++----- bsp/coreip-e31-arty/metal-platform.h | 7 +----- bsp/coreip-e31-arty/metal.default.lds | 2 +- bsp/coreip-e31-arty/metal.h | 17 ++++++++++---- bsp/coreip-e31-arty/metal.ramrodata.lds | 2 +- bsp/coreip-e31-arty/metal.scratchpad.lds | 2 +- bsp/coreip-e31-arty/settings.mk | 2 +- bsp/coreip-e31-rtl/metal-inline.h | 8 ++----- bsp/coreip-e31-rtl/metal-platform.h | 7 +----- bsp/coreip-e31-rtl/metal.default.lds | 2 +- bsp/coreip-e31-rtl/metal.h | 17 ++++++++++---- bsp/coreip-e31-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-e31-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-e31-rtl/settings.mk | 2 +- bsp/coreip-e34-arty/metal-inline.h | 8 ++----- bsp/coreip-e34-arty/metal-platform.h | 7 +----- bsp/coreip-e34-arty/metal.default.lds | 2 +- bsp/coreip-e34-arty/metal.h | 17 ++++++++++---- bsp/coreip-e34-arty/metal.ramrodata.lds | 2 +- bsp/coreip-e34-arty/metal.scratchpad.lds | 2 +- bsp/coreip-e34-arty/settings.mk | 2 +- bsp/coreip-e34-rtl/metal-inline.h | 8 ++----- bsp/coreip-e34-rtl/metal-platform.h | 7 +----- bsp/coreip-e34-rtl/metal.default.lds | 2 +- bsp/coreip-e34-rtl/metal.h | 17 ++++++++++---- bsp/coreip-e34-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-e34-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-e34-rtl/settings.mk | 2 +- bsp/coreip-e76-arty/metal-inline.h | 8 ++----- bsp/coreip-e76-arty/metal-platform.h | 7 +----- bsp/coreip-e76-arty/metal.default.lds | 2 +- bsp/coreip-e76-arty/metal.h | 17 ++++++++++---- bsp/coreip-e76-arty/metal.ramrodata.lds | 2 +- bsp/coreip-e76-arty/metal.scratchpad.lds | 2 +- bsp/coreip-e76-arty/settings.mk | 2 +- bsp/coreip-e76-rtl/metal-inline.h | 8 ++----- bsp/coreip-e76-rtl/metal-platform.h | 7 +----- bsp/coreip-e76-rtl/metal.default.lds | 2 +- bsp/coreip-e76-rtl/metal.h | 17 ++++++++++---- bsp/coreip-e76-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-e76-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-e76-rtl/settings.mk | 2 +- bsp/coreip-s51-arty/metal-inline.h | 8 ++----- bsp/coreip-s51-arty/metal-platform.h | 7 +----- bsp/coreip-s51-arty/metal.default.lds | 2 +- bsp/coreip-s51-arty/metal.h | 17 ++++++++++---- bsp/coreip-s51-arty/metal.ramrodata.lds | 2 +- bsp/coreip-s51-arty/metal.scratchpad.lds | 2 +- bsp/coreip-s51-arty/settings.mk | 2 +- bsp/coreip-s51-rtl/metal-inline.h | 8 ++----- bsp/coreip-s51-rtl/metal-platform.h | 7 +----- bsp/coreip-s51-rtl/metal.default.lds | 2 +- bsp/coreip-s51-rtl/metal.h | 17 ++++++++++---- bsp/coreip-s51-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-s51-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-s51-rtl/settings.mk | 2 +- bsp/coreip-s54-arty/metal-inline.h | 8 ++----- bsp/coreip-s54-arty/metal-platform.h | 7 +----- bsp/coreip-s54-arty/metal.default.lds | 2 +- bsp/coreip-s54-arty/metal.h | 17 ++++++++++---- bsp/coreip-s54-arty/metal.ramrodata.lds | 2 +- bsp/coreip-s54-arty/metal.scratchpad.lds | 2 +- bsp/coreip-s54-arty/settings.mk | 2 +- bsp/coreip-s54-rtl/metal-inline.h | 8 ++----- bsp/coreip-s54-rtl/metal-platform.h | 7 +----- bsp/coreip-s54-rtl/metal.default.lds | 2 +- bsp/coreip-s54-rtl/metal.h | 17 ++++++++++---- bsp/coreip-s54-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-s54-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-s54-rtl/settings.mk | 2 +- bsp/coreip-s76-arty/metal-inline.h | 8 ++----- bsp/coreip-s76-arty/metal-platform.h | 7 +----- bsp/coreip-s76-arty/metal.default.lds | 2 +- bsp/coreip-s76-arty/metal.h | 17 ++++++++++---- bsp/coreip-s76-arty/metal.ramrodata.lds | 2 +- bsp/coreip-s76-arty/metal.scratchpad.lds | 2 +- bsp/coreip-s76-arty/settings.mk | 2 +- bsp/coreip-s76-rtl/metal-inline.h | 8 ++----- bsp/coreip-s76-rtl/metal-platform.h | 7 +----- bsp/coreip-s76-rtl/metal.default.lds | 2 +- bsp/coreip-s76-rtl/metal.h | 17 ++++++++++---- bsp/coreip-s76-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-s76-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-s76-rtl/settings.mk | 2 +- bsp/coreip-u54-rtl/metal-inline.h | 8 ++----- bsp/coreip-u54-rtl/metal-platform.h | 7 +----- bsp/coreip-u54-rtl/metal.default.lds | 2 +- bsp/coreip-u54-rtl/metal.h | 17 ++++++++++---- bsp/coreip-u54-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-u54-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-u54-rtl/settings.mk | 2 +- bsp/coreip-u54mc-rtl/metal-inline.h | 8 ++----- bsp/coreip-u54mc-rtl/metal-platform.h | 7 +----- bsp/coreip-u54mc-rtl/metal.default.lds | 2 +- bsp/coreip-u54mc-rtl/metal.h | 29 ++++++++++++++++++++---- bsp/coreip-u54mc-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-u54mc-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-u54mc-rtl/settings.mk | 2 +- bsp/freedom-e310-arty/metal-inline.h | 3 ++- bsp/freedom-e310-arty/metal-platform.h | 2 +- bsp/freedom-e310-arty/metal.default.lds | 2 +- bsp/freedom-e310-arty/metal.h | 12 +++++++++- bsp/freedom-e310-arty/metal.ramrodata.lds | 2 +- bsp/freedom-e310-arty/metal.scratchpad.lds | 2 +- bsp/freedom-e310-arty/settings.mk | 2 +- bsp/sifive-hifive-unleashed/metal-inline.h | 8 ++----- bsp/sifive-hifive-unleashed/metal-platform.h | 15 +++++------- bsp/sifive-hifive-unleashed/metal.default.lds | 2 +- bsp/sifive-hifive-unleashed/metal.h | 29 ++++++++++++++++++++---- bsp/sifive-hifive-unleashed/metal.ramrodata.lds | 2 +- bsp/sifive-hifive-unleashed/metal.scratchpad.lds | 2 +- bsp/sifive-hifive1-revb/metal-inline.h | 8 ++----- bsp/sifive-hifive1-revb/metal-platform.h | 7 +----- bsp/sifive-hifive1-revb/metal.default.lds | 2 +- bsp/sifive-hifive1-revb/metal.h | 17 ++++++++++---- bsp/sifive-hifive1-revb/metal.ramrodata.lds | 2 +- bsp/sifive-hifive1-revb/metal.scratchpad.lds | 2 +- bsp/sifive-hifive1-revb/settings.mk | 2 +- bsp/sifive-hifive1/metal-inline.h | 3 ++- bsp/sifive-hifive1/metal-platform.h | 2 +- bsp/sifive-hifive1/metal.default.lds | 2 +- bsp/sifive-hifive1/metal.h | 12 +++++++++- bsp/sifive-hifive1/metal.ramrodata.lds | 2 +- bsp/sifive-hifive1/metal.scratchpad.lds | 2 +- bsp/sifive-hifive1/settings.mk | 2 +- 167 files changed, 500 insertions(+), 430 deletions(-) (limited to 'bsp') diff --git a/bsp/coreip-e20-arty/metal-inline.h b/bsp/coreip-e20-arty/metal-inline.h index 8170f13..682d70d 100644 --- a/bsp/coreip-e20-arty/metal-inline.h +++ b/bsp/coreip-e20-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -25,6 +25,7 @@ extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock * /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/coreip-e20-arty/metal-platform.h b/bsp/coreip-e20-arty/metal-platform.h index 0e58533..a31682d 100644 --- a/bsp/coreip-e20-arty/metal-platform.h +++ b/bsp/coreip-e20-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E20_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-e20-arty/metal.default.lds b/bsp/coreip-e20-arty/metal.default.lds index 2516d37..de7d8d6 100644 --- a/bsp/coreip-e20-arty/metal.default.lds +++ b/bsp/coreip-e20-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e20-arty/metal.h b/bsp/coreip-e20-arty/metal.h index 5e182ab..8a4b3dd 100644 --- a/bsp/coreip-e20-arty/metal.h +++ b/bsp/coreip-e20-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -190,6 +190,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/coreip-e20-arty/metal.ramrodata.lds b/bsp/coreip-e20-arty/metal.ramrodata.lds index 0290158..17b3e25 100644 --- a/bsp/coreip-e20-arty/metal.ramrodata.lds +++ b/bsp/coreip-e20-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e20-arty/metal.scratchpad.lds b/bsp/coreip-e20-arty/metal.scratchpad.lds index 5d4cd7b..eb571c0 100644 --- a/bsp/coreip-e20-arty/metal.scratchpad.lds +++ b/bsp/coreip-e20-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e20-arty/settings.mk b/bsp/coreip-e20-arty/settings.mk index 5a405fe..85c4141 100644 --- a/bsp/coreip-e20-arty/settings.mk +++ b/bsp/coreip-e20-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-09 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imc diff --git a/bsp/coreip-e20-rtl/metal-inline.h b/bsp/coreip-e20-rtl/metal-inline.h index 1f2399d..5bd0417 100644 --- a/bsp/coreip-e20-rtl/metal-inline.h +++ b/bsp/coreip-e20-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -24,6 +24,7 @@ /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/coreip-e20-rtl/metal-platform.h b/bsp/coreip-e20-rtl/metal-platform.h index b4f13ec..02b0ad9 100644 --- a/bsp/coreip-e20-rtl/metal-platform.h +++ b/bsp/coreip-e20-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E20_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-e20-rtl/metal.default.lds b/bsp/coreip-e20-rtl/metal.default.lds index c95e179..af982c6 100644 --- a/bsp/coreip-e20-rtl/metal.default.lds +++ b/bsp/coreip-e20-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e20-rtl/metal.h b/bsp/coreip-e20-rtl/metal.h index 68d33ad..1f38a0f 100644 --- a/bsp/coreip-e20-rtl/metal.h +++ b/bsp/coreip-e20-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -117,6 +117,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/coreip-e20-rtl/metal.ramrodata.lds b/bsp/coreip-e20-rtl/metal.ramrodata.lds index 02f50c8..782640e 100644 --- a/bsp/coreip-e20-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e20-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e20-rtl/metal.scratchpad.lds b/bsp/coreip-e20-rtl/metal.scratchpad.lds index c95e179..af982c6 100644 --- a/bsp/coreip-e20-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e20-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-09 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e20-rtl/settings.mk b/bsp/coreip-e20-rtl/settings.mk index 6520e6d..8c8cfc0 100644 --- a/bsp/coreip-e20-rtl/settings.mk +++ b/bsp/coreip-e20-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-09 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imc diff --git a/bsp/coreip-e21-arty/metal-inline.h b/bsp/coreip-e21-arty/metal-inline.h index 0f167d5..37937d3 100644 --- a/bsp/coreip-e21-arty/metal-inline.h +++ b/bsp/coreip-e21-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -25,6 +25,7 @@ extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock * /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -173,11 +174,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, diff --git a/bsp/coreip-e21-arty/metal-platform.h b/bsp/coreip-e21-arty/metal-platform.h index 75dc2dd..adbfb15 100644 --- a/bsp/coreip-e21-arty/metal-platform.h +++ b/bsp/coreip-e21-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E21_ARTY__METAL_PLATFORM_H @@ -12,11 +12,6 @@ #define METAL_FIXED_CLOCK -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 4UL - -#define METAL_RISCV_PMP - /* From interrupt_controller@2000000 */ #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL #define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL diff --git a/bsp/coreip-e21-arty/metal.default.lds b/bsp/coreip-e21-arty/metal.default.lds index 0b7a37a..b7665dd 100644 --- a/bsp/coreip-e21-arty/metal.default.lds +++ b/bsp/coreip-e21-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e21-arty/metal.h b/bsp/coreip-e21-arty/metal.h index 89b2931..8ef7fc6 100644 --- a/bsp/coreip-e21-arty/metal.h +++ b/bsp/coreip-e21-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0; struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; @@ -194,6 +194,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 4; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -1226,8 +1236,7 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e21-arty/metal.ramrodata.lds b/bsp/coreip-e21-arty/metal.ramrodata.lds index e1e793f..54b0c8e 100644 --- a/bsp/coreip-e21-arty/metal.ramrodata.lds +++ b/bsp/coreip-e21-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e21-arty/metal.scratchpad.lds b/bsp/coreip-e21-arty/metal.scratchpad.lds index e986066..912117d 100644 --- a/bsp/coreip-e21-arty/metal.scratchpad.lds +++ b/bsp/coreip-e21-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk index b9be584..d7bf600 100644 --- a/bsp/coreip-e21-arty/settings.mk +++ b/bsp/coreip-e21-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/coreip-e21-rtl/metal-inline.h b/bsp/coreip-e21-rtl/metal-inline.h index a117144..9c4c7ef 100644 --- a/bsp/coreip-e21-rtl/metal-inline.h +++ b/bsp/coreip-e21-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -24,6 +24,7 @@ /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -131,11 +132,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, diff --git a/bsp/coreip-e21-rtl/metal-platform.h b/bsp/coreip-e21-rtl/metal-platform.h index baf85fc..7069709 100644 --- a/bsp/coreip-e21-rtl/metal-platform.h +++ b/bsp/coreip-e21-rtl/metal-platform.h @@ -1,17 +1,12 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E21_RTL__METAL_PLATFORM_H #define COREIP_E21_RTL__METAL_PLATFORM_H -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From interrupt_controller@2000000 */ #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL #define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL diff --git a/bsp/coreip-e21-rtl/metal.default.lds b/bsp/coreip-e21-rtl/metal.default.lds index d021e81..b1c05ca 100644 --- a/bsp/coreip-e21-rtl/metal.default.lds +++ b/bsp/coreip-e21-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e21-rtl/metal.h b/bsp/coreip-e21-rtl/metal.h index 38b19a4..1c46492 100644 --- a/bsp/coreip-e21-rtl/metal.h +++ b/bsp/coreip-e21-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -80,7 +80,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0; struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; @@ -123,6 +123,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 4; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -694,8 +704,7 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e21-rtl/metal.ramrodata.lds b/bsp/coreip-e21-rtl/metal.ramrodata.lds index 199cc1f..59bfadc 100644 --- a/bsp/coreip-e21-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e21-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e21-rtl/metal.scratchpad.lds b/bsp/coreip-e21-rtl/metal.scratchpad.lds index 8bea50d..ccd53eb 100644 --- a/bsp/coreip-e21-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e21-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e21-rtl/settings.mk b/bsp/coreip-e21-rtl/settings.mk index bb8d89a..85e5a58 100644 --- a/bsp/coreip-e21-rtl/settings.mk +++ b/bsp/coreip-e21-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/coreip-e24-arty/metal-inline.h b/bsp/coreip-e24-arty/metal-inline.h index bbe456e..0c359b2 100644 --- a/bsp/coreip-e24-arty/metal-inline.h +++ b/bsp/coreip-e24-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -25,6 +25,7 @@ extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock * /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -173,11 +174,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, diff --git a/bsp/coreip-e24-arty/metal-platform.h b/bsp/coreip-e24-arty/metal-platform.h index 1a3bd88..ec9b9e1 100644 --- a/bsp/coreip-e24-arty/metal-platform.h +++ b/bsp/coreip-e24-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E24_ARTY__METAL_PLATFORM_H @@ -12,11 +12,6 @@ #define METAL_FIXED_CLOCK -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 4UL - -#define METAL_RISCV_PMP - /* From interrupt_controller@2000000 */ #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL #define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL diff --git a/bsp/coreip-e24-arty/metal.default.lds b/bsp/coreip-e24-arty/metal.default.lds index 0b7a37a..b7665dd 100644 --- a/bsp/coreip-e24-arty/metal.default.lds +++ b/bsp/coreip-e24-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e24-arty/metal.h b/bsp/coreip-e24-arty/metal.h index 772ac57..2725154 100644 --- a/bsp/coreip-e24-arty/metal.h +++ b/bsp/coreip-e24-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0; struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; @@ -194,6 +194,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 4; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -1226,8 +1236,7 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e24-arty/metal.ramrodata.lds b/bsp/coreip-e24-arty/metal.ramrodata.lds index e1e793f..54b0c8e 100644 --- a/bsp/coreip-e24-arty/metal.ramrodata.lds +++ b/bsp/coreip-e24-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e24-arty/metal.scratchpad.lds b/bsp/coreip-e24-arty/metal.scratchpad.lds index e986066..912117d 100644 --- a/bsp/coreip-e24-arty/metal.scratchpad.lds +++ b/bsp/coreip-e24-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e24-arty/settings.mk b/bsp/coreip-e24-arty/settings.mk index 115db75..429208f 100644 --- a/bsp/coreip-e24-arty/settings.mk +++ b/bsp/coreip-e24-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-e24-rtl/metal-inline.h b/bsp/coreip-e24-rtl/metal-inline.h index dd34d93..460e9d3 100644 --- a/bsp/coreip-e24-rtl/metal-inline.h +++ b/bsp/coreip-e24-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -24,6 +24,7 @@ /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -131,11 +132,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, diff --git a/bsp/coreip-e24-rtl/metal-platform.h b/bsp/coreip-e24-rtl/metal-platform.h index dabc75f..7806168 100644 --- a/bsp/coreip-e24-rtl/metal-platform.h +++ b/bsp/coreip-e24-rtl/metal-platform.h @@ -1,17 +1,12 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E24_RTL__METAL_PLATFORM_H #define COREIP_E24_RTL__METAL_PLATFORM_H -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From interrupt_controller@2000000 */ #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL #define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL diff --git a/bsp/coreip-e24-rtl/metal.default.lds b/bsp/coreip-e24-rtl/metal.default.lds index d021e81..b1c05ca 100644 --- a/bsp/coreip-e24-rtl/metal.default.lds +++ b/bsp/coreip-e24-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e24-rtl/metal.h b/bsp/coreip-e24-rtl/metal.h index 6d97dbd..bbe0508 100644 --- a/bsp/coreip-e24-rtl/metal.h +++ b/bsp/coreip-e24-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -80,7 +80,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0; struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; @@ -123,6 +123,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 4; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -694,8 +704,7 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e24-rtl/metal.ramrodata.lds b/bsp/coreip-e24-rtl/metal.ramrodata.lds index 199cc1f..59bfadc 100644 --- a/bsp/coreip-e24-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e24-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e24-rtl/metal.scratchpad.lds b/bsp/coreip-e24-rtl/metal.scratchpad.lds index 8bea50d..ccd53eb 100644 --- a/bsp/coreip-e24-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e24-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e24-rtl/settings.mk b/bsp/coreip-e24-rtl/settings.mk index 4d6b13e..942bc62 100644 --- a/bsp/coreip-e24-rtl/settings.mk +++ b/bsp/coreip-e24-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-e31-arty/metal-inline.h b/bsp/coreip-e31-arty/metal-inline.h index fe89e39..88b82bc 100644 --- a/bsp/coreip-e31-arty/metal-inline.h +++ b/bsp/coreip-e31-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -188,11 +189,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-e31-arty/metal-platform.h b/bsp/coreip-e31-arty/metal-platform.h index c4c1b37..e01cbdb 100644 --- a/bsp/coreip-e31-arty/metal-platform.h +++ b/bsp/coreip-e31-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E31_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e31-arty/metal.default.lds b/bsp/coreip-e31-arty/metal.default.lds index 82a199e..53a32f1 100644 --- a/bsp/coreip-e31-arty/metal.default.lds +++ b/bsp/coreip-e31-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e31-arty/metal.h b/bsp/coreip-e31-arty/metal.h index f3a6fb3..eb0cc1e 100644 --- a/bsp/coreip-e31-arty/metal.h +++ b/bsp/coreip-e31-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -109,7 +109,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -260,6 +260,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -946,8 +956,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-e31-arty/metal.ramrodata.lds b/bsp/coreip-e31-arty/metal.ramrodata.lds index 22eeb0a..c684be1 100644 --- a/bsp/coreip-e31-arty/metal.ramrodata.lds +++ b/bsp/coreip-e31-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e31-arty/metal.scratchpad.lds b/bsp/coreip-e31-arty/metal.scratchpad.lds index 808429b..6b224a0 100644 --- a/bsp/coreip-e31-arty/metal.scratchpad.lds +++ b/bsp/coreip-e31-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk index b9be584..d7bf600 100644 --- a/bsp/coreip-e31-arty/settings.mk +++ b/bsp/coreip-e31-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/coreip-e31-rtl/metal-inline.h b/bsp/coreip-e31-rtl/metal-inline.h index 173385b..692078e 100644 --- a/bsp/coreip-e31-rtl/metal-inline.h +++ b/bsp/coreip-e31-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -29,6 +29,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -150,11 +151,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-e31-rtl/metal-platform.h b/bsp/coreip-e31-rtl/metal-platform.h index 43c8148..571736f 100644 --- a/bsp/coreip-e31-rtl/metal-platform.h +++ b/bsp/coreip-e31-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E31_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e31-rtl/metal.default.lds b/bsp/coreip-e31-rtl/metal.default.lds index d4a124f..f29e650 100644 --- a/bsp/coreip-e31-rtl/metal.default.lds +++ b/bsp/coreip-e31-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e31-rtl/metal.h b/bsp/coreip-e31-rtl/metal.h index 22fc0eb..f869d80 100644 --- a/bsp/coreip-e31-rtl/metal.h +++ b/bsp/coreip-e31-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -195,6 +195,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -833,8 +843,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-e31-rtl/metal.ramrodata.lds b/bsp/coreip-e31-rtl/metal.ramrodata.lds index 6f9d52e..fd9fded 100644 --- a/bsp/coreip-e31-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e31-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e31-rtl/metal.scratchpad.lds b/bsp/coreip-e31-rtl/metal.scratchpad.lds index d711300..99dfa4e 100644 --- a/bsp/coreip-e31-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e31-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk index bb8d89a..85e5a58 100644 --- a/bsp/coreip-e31-rtl/settings.mk +++ b/bsp/coreip-e31-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/coreip-e34-arty/metal-inline.h b/bsp/coreip-e34-arty/metal-inline.h index 1ba2da5..a1478e2 100644 --- a/bsp/coreip-e34-arty/metal-inline.h +++ b/bsp/coreip-e34-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -188,11 +189,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-e34-arty/metal-platform.h b/bsp/coreip-e34-arty/metal-platform.h index c2cacc4..a0c3791 100644 --- a/bsp/coreip-e34-arty/metal-platform.h +++ b/bsp/coreip-e34-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E34_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e34-arty/metal.default.lds b/bsp/coreip-e34-arty/metal.default.lds index 82a199e..53a32f1 100644 --- a/bsp/coreip-e34-arty/metal.default.lds +++ b/bsp/coreip-e34-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e34-arty/metal.h b/bsp/coreip-e34-arty/metal.h index 949a75c..4b11daf 100644 --- a/bsp/coreip-e34-arty/metal.h +++ b/bsp/coreip-e34-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -109,7 +109,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -260,6 +260,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -946,8 +956,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-e34-arty/metal.ramrodata.lds b/bsp/coreip-e34-arty/metal.ramrodata.lds index 22eeb0a..c684be1 100644 --- a/bsp/coreip-e34-arty/metal.ramrodata.lds +++ b/bsp/coreip-e34-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e34-arty/metal.scratchpad.lds b/bsp/coreip-e34-arty/metal.scratchpad.lds index 808429b..6b224a0 100644 --- a/bsp/coreip-e34-arty/metal.scratchpad.lds +++ b/bsp/coreip-e34-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e34-arty/settings.mk b/bsp/coreip-e34-arty/settings.mk index 115db75..429208f 100644 --- a/bsp/coreip-e34-arty/settings.mk +++ b/bsp/coreip-e34-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-e34-rtl/metal-inline.h b/bsp/coreip-e34-rtl/metal-inline.h index 6ebb5a0..30e90fa 100644 --- a/bsp/coreip-e34-rtl/metal-inline.h +++ b/bsp/coreip-e34-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -29,6 +29,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -150,11 +151,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-e34-rtl/metal-platform.h b/bsp/coreip-e34-rtl/metal-platform.h index 8ac399d..7abc816 100644 --- a/bsp/coreip-e34-rtl/metal-platform.h +++ b/bsp/coreip-e34-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E34_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e34-rtl/metal.default.lds b/bsp/coreip-e34-rtl/metal.default.lds index d4a124f..f29e650 100644 --- a/bsp/coreip-e34-rtl/metal.default.lds +++ b/bsp/coreip-e34-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e34-rtl/metal.h b/bsp/coreip-e34-rtl/metal.h index de80e1b..2019930 100644 --- a/bsp/coreip-e34-rtl/metal.h +++ b/bsp/coreip-e34-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -195,6 +195,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -833,8 +843,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-e34-rtl/metal.ramrodata.lds b/bsp/coreip-e34-rtl/metal.ramrodata.lds index 6f9d52e..fd9fded 100644 --- a/bsp/coreip-e34-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e34-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e34-rtl/metal.scratchpad.lds b/bsp/coreip-e34-rtl/metal.scratchpad.lds index d711300..99dfa4e 100644 --- a/bsp/coreip-e34-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e34-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e34-rtl/settings.mk b/bsp/coreip-e34-rtl/settings.mk index 4d6b13e..942bc62 100644 --- a/bsp/coreip-e34-rtl/settings.mk +++ b/bsp/coreip-e34-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-e76-arty/metal-inline.h b/bsp/coreip-e76-arty/metal-inline.h index bd8e58b..79d9511 100644 --- a/bsp/coreip-e76-arty/metal-inline.h +++ b/bsp/coreip-e76-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -174,11 +175,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-e76-arty/metal-platform.h b/bsp/coreip-e76-arty/metal-platform.h index d99248d..229fecc 100644 --- a/bsp/coreip-e76-arty/metal-platform.h +++ b/bsp/coreip-e76-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E76_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e76-arty/metal.default.lds b/bsp/coreip-e76-arty/metal.default.lds index 5f18721..b9fd8c7 100644 --- a/bsp/coreip-e76-arty/metal.default.lds +++ b/bsp/coreip-e76-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h index 21a9416..a48daa4 100644 --- a/bsp/coreip-e76-arty/metal.h +++ b/bsp/coreip-e76-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -106,7 +106,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -257,6 +257,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -891,8 +901,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-e76-arty/metal.ramrodata.lds b/bsp/coreip-e76-arty/metal.ramrodata.lds index 2399c34..5a48635 100644 --- a/bsp/coreip-e76-arty/metal.ramrodata.lds +++ b/bsp/coreip-e76-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e76-arty/metal.scratchpad.lds b/bsp/coreip-e76-arty/metal.scratchpad.lds index f218377..5abe56e 100644 --- a/bsp/coreip-e76-arty/metal.scratchpad.lds +++ b/bsp/coreip-e76-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk index 115db75..429208f 100644 --- a/bsp/coreip-e76-arty/settings.mk +++ b/bsp/coreip-e76-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-e76-rtl/metal-inline.h b/bsp/coreip-e76-rtl/metal-inline.h index fe18ce9..e549be9 100644 --- a/bsp/coreip-e76-rtl/metal-inline.h +++ b/bsp/coreip-e76-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -29,6 +29,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -125,11 +126,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-e76-rtl/metal-platform.h b/bsp/coreip-e76-rtl/metal-platform.h index fc2e618..758b785 100644 --- a/bsp/coreip-e76-rtl/metal-platform.h +++ b/bsp/coreip-e76-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E76_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e76-rtl/metal.default.lds b/bsp/coreip-e76-rtl/metal.default.lds index 84b0c14..1212a6e 100644 --- a/bsp/coreip-e76-rtl/metal.default.lds +++ b/bsp/coreip-e76-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e76-rtl/metal.h b/bsp/coreip-e76-rtl/metal.h index 84e5823..34d2545 100644 --- a/bsp/coreip-e76-rtl/metal.h +++ b/bsp/coreip-e76-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -89,7 +89,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -185,6 +185,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -746,8 +756,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-e76-rtl/metal.ramrodata.lds b/bsp/coreip-e76-rtl/metal.ramrodata.lds index 60429dd..198bf29 100644 --- a/bsp/coreip-e76-rtl/metal.ramrodata.lds +++ b/bsp/coreip-e76-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e76-rtl/metal.scratchpad.lds b/bsp/coreip-e76-rtl/metal.scratchpad.lds index 84b0c14..1212a6e 100644 --- a/bsp/coreip-e76-rtl/metal.scratchpad.lds +++ b/bsp/coreip-e76-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e76-rtl/settings.mk b/bsp/coreip-e76-rtl/settings.mk index 18bea9e..9c9e85d 100644 --- a/bsp/coreip-e76-rtl/settings.mk +++ b/bsp/coreip-e76-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imafc diff --git a/bsp/coreip-s51-arty/metal-inline.h b/bsp/coreip-s51-arty/metal-inline.h index 7fe8125..2c679a4 100644 --- a/bsp/coreip-s51-arty/metal-inline.h +++ b/bsp/coreip-s51-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -188,11 +189,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-s51-arty/metal-platform.h b/bsp/coreip-s51-arty/metal-platform.h index 2d97f6c..1defcb6 100644 --- a/bsp/coreip-s51-arty/metal-platform.h +++ b/bsp/coreip-s51-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_S51_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s51-arty/metal.default.lds b/bsp/coreip-s51-arty/metal.default.lds index 82a199e..53a32f1 100644 --- a/bsp/coreip-s51-arty/metal.default.lds +++ b/bsp/coreip-s51-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s51-arty/metal.h b/bsp/coreip-s51-arty/metal.h index 9d1a901..3365d5e 100644 --- a/bsp/coreip-s51-arty/metal.h +++ b/bsp/coreip-s51-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -109,7 +109,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -260,6 +260,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -946,8 +956,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-s51-arty/metal.ramrodata.lds b/bsp/coreip-s51-arty/metal.ramrodata.lds index 22eeb0a..c684be1 100644 --- a/bsp/coreip-s51-arty/metal.ramrodata.lds +++ b/bsp/coreip-s51-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s51-arty/metal.scratchpad.lds b/bsp/coreip-s51-arty/metal.scratchpad.lds index 808429b..6b224a0 100644 --- a/bsp/coreip-s51-arty/metal.scratchpad.lds +++ b/bsp/coreip-s51-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s51-arty/settings.mk b/bsp/coreip-s51-arty/settings.mk index 19205af..639de93 100644 --- a/bsp/coreip-s51-arty/settings.mk +++ b/bsp/coreip-s51-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv64imac diff --git a/bsp/coreip-s51-rtl/metal-inline.h b/bsp/coreip-s51-rtl/metal-inline.h index 06b7384..af290b5 100644 --- a/bsp/coreip-s51-rtl/metal-inline.h +++ b/bsp/coreip-s51-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -29,6 +29,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -150,11 +151,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-s51-rtl/metal-platform.h b/bsp/coreip-s51-rtl/metal-platform.h index 009cad9..e0074ed 100644 --- a/bsp/coreip-s51-rtl/metal-platform.h +++ b/bsp/coreip-s51-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_S51_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s51-rtl/metal.default.lds b/bsp/coreip-s51-rtl/metal.default.lds index e68e937..becfaf5 100644 --- a/bsp/coreip-s51-rtl/metal.default.lds +++ b/bsp/coreip-s51-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s51-rtl/metal.h b/bsp/coreip-s51-rtl/metal.h index 6cf2856..e7922b9 100644 --- a/bsp/coreip-s51-rtl/metal.h +++ b/bsp/coreip-s51-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -195,6 +195,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -833,8 +843,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-s51-rtl/metal.ramrodata.lds b/bsp/coreip-s51-rtl/metal.ramrodata.lds index 448d7ed..79a9105 100644 --- a/bsp/coreip-s51-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s51-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s51-rtl/metal.scratchpad.lds b/bsp/coreip-s51-rtl/metal.scratchpad.lds index 4d43737..1b0941c 100644 --- a/bsp/coreip-s51-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s51-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s51-rtl/settings.mk b/bsp/coreip-s51-rtl/settings.mk index 6af5958..380e38e 100644 --- a/bsp/coreip-s51-rtl/settings.mk +++ b/bsp/coreip-s51-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv64imac diff --git a/bsp/coreip-s54-arty/metal-inline.h b/bsp/coreip-s54-arty/metal-inline.h index fee9bcd..6ec413d 100644 --- a/bsp/coreip-s54-arty/metal-inline.h +++ b/bsp/coreip-s54-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -188,11 +189,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-s54-arty/metal-platform.h b/bsp/coreip-s54-arty/metal-platform.h index 7f1e2d0..1767e31 100644 --- a/bsp/coreip-s54-arty/metal-platform.h +++ b/bsp/coreip-s54-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_S54_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s54-arty/metal.default.lds b/bsp/coreip-s54-arty/metal.default.lds index 82a199e..53a32f1 100644 --- a/bsp/coreip-s54-arty/metal.default.lds +++ b/bsp/coreip-s54-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s54-arty/metal.h b/bsp/coreip-s54-arty/metal.h index fd36163..ecff95c 100644 --- a/bsp/coreip-s54-arty/metal.h +++ b/bsp/coreip-s54-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -109,7 +109,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -260,6 +260,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -946,8 +956,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-s54-arty/metal.ramrodata.lds b/bsp/coreip-s54-arty/metal.ramrodata.lds index 22eeb0a..c684be1 100644 --- a/bsp/coreip-s54-arty/metal.ramrodata.lds +++ b/bsp/coreip-s54-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s54-arty/metal.scratchpad.lds b/bsp/coreip-s54-arty/metal.scratchpad.lds index 808429b..6b224a0 100644 --- a/bsp/coreip-s54-arty/metal.scratchpad.lds +++ b/bsp/coreip-s54-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s54-arty/settings.mk b/bsp/coreip-s54-arty/settings.mk index 4ce0f71..4b9dfb0 100644 --- a/bsp/coreip-s54-arty/settings.mk +++ b/bsp/coreip-s54-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv64imafdc diff --git a/bsp/coreip-s54-rtl/metal-inline.h b/bsp/coreip-s54-rtl/metal-inline.h index 402ee7e..9fe2c39 100644 --- a/bsp/coreip-s54-rtl/metal-inline.h +++ b/bsp/coreip-s54-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -29,6 +29,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -150,11 +151,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/coreip-s54-rtl/metal-platform.h b/bsp/coreip-s54-rtl/metal-platform.h index 3906b83..d5f6de8 100644 --- a/bsp/coreip-s54-rtl/metal-platform.h +++ b/bsp/coreip-s54-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_S54_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s54-rtl/metal.default.lds b/bsp/coreip-s54-rtl/metal.default.lds index e68e937..becfaf5 100644 --- a/bsp/coreip-s54-rtl/metal.default.lds +++ b/bsp/coreip-s54-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s54-rtl/metal.h b/bsp/coreip-s54-rtl/metal.h index 6d8e8e1..c47f29e 100644 --- a/bsp/coreip-s54-rtl/metal.h +++ b/bsp/coreip-s54-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -195,6 +195,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -833,8 +843,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/coreip-s54-rtl/metal.ramrodata.lds b/bsp/coreip-s54-rtl/metal.ramrodata.lds index 448d7ed..79a9105 100644 --- a/bsp/coreip-s54-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s54-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s54-rtl/metal.scratchpad.lds b/bsp/coreip-s54-rtl/metal.scratchpad.lds index 4d43737..1b0941c 100644 --- a/bsp/coreip-s54-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s54-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s54-rtl/settings.mk b/bsp/coreip-s54-rtl/settings.mk index c7a4614..389d403 100644 --- a/bsp/coreip-s54-rtl/settings.mk +++ b/bsp/coreip-s54-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv64imafdc diff --git a/bsp/coreip-s76-arty/metal-inline.h b/bsp/coreip-s76-arty/metal-inline.h index 6d4d486..a4e44af 100644 --- a/bsp/coreip-s76-arty/metal-inline.h +++ b/bsp/coreip-s76-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -174,11 +175,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-s76-arty/metal-platform.h b/bsp/coreip-s76-arty/metal-platform.h index eda81f7..1e72316 100644 --- a/bsp/coreip-s76-arty/metal-platform.h +++ b/bsp/coreip-s76-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_S76_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s76-arty/metal.default.lds b/bsp/coreip-s76-arty/metal.default.lds index 5f18721..b9fd8c7 100644 --- a/bsp/coreip-s76-arty/metal.default.lds +++ b/bsp/coreip-s76-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s76-arty/metal.h b/bsp/coreip-s76-arty/metal.h index 7c64fc7..d948150 100644 --- a/bsp/coreip-s76-arty/metal.h +++ b/bsp/coreip-s76-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -106,7 +106,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -257,6 +257,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -891,8 +901,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-s76-arty/metal.ramrodata.lds b/bsp/coreip-s76-arty/metal.ramrodata.lds index 2399c34..5a48635 100644 --- a/bsp/coreip-s76-arty/metal.ramrodata.lds +++ b/bsp/coreip-s76-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s76-arty/metal.scratchpad.lds b/bsp/coreip-s76-arty/metal.scratchpad.lds index f218377..5abe56e 100644 --- a/bsp/coreip-s76-arty/metal.scratchpad.lds +++ b/bsp/coreip-s76-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s76-arty/settings.mk b/bsp/coreip-s76-arty/settings.mk index 4ce0f71..4b9dfb0 100644 --- a/bsp/coreip-s76-arty/settings.mk +++ b/bsp/coreip-s76-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv64imafdc diff --git a/bsp/coreip-s76-rtl/metal-inline.h b/bsp/coreip-s76-rtl/metal-inline.h index 1d139e1..9ab68d4 100644 --- a/bsp/coreip-s76-rtl/metal-inline.h +++ b/bsp/coreip-s76-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -29,6 +29,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -125,11 +126,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-s76-rtl/metal-platform.h b/bsp/coreip-s76-rtl/metal-platform.h index 2d911a5..4aa8776 100644 --- a/bsp/coreip-s76-rtl/metal-platform.h +++ b/bsp/coreip-s76-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef COREIP_S76_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-s76-rtl/metal.default.lds b/bsp/coreip-s76-rtl/metal.default.lds index 84b0c14..3595f92 100644 --- a/bsp/coreip-s76-rtl/metal.default.lds +++ b/bsp/coreip-s76-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s76-rtl/metal.h b/bsp/coreip-s76-rtl/metal.h index 3221ed3..2a7145c 100644 --- a/bsp/coreip-s76-rtl/metal.h +++ b/bsp/coreip-s76-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -89,7 +89,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -185,6 +185,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -746,8 +756,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-s76-rtl/metal.ramrodata.lds b/bsp/coreip-s76-rtl/metal.ramrodata.lds index 60429dd..e7c0478 100644 --- a/bsp/coreip-s76-rtl/metal.ramrodata.lds +++ b/bsp/coreip-s76-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s76-rtl/metal.scratchpad.lds b/bsp/coreip-s76-rtl/metal.scratchpad.lds index 84b0c14..3595f92 100644 --- a/bsp/coreip-s76-rtl/metal.scratchpad.lds +++ b/bsp/coreip-s76-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-s76-rtl/settings.mk b/bsp/coreip-s76-rtl/settings.mk index c7a4614..53c575a 100644 --- a/bsp/coreip-s76-rtl/settings.mk +++ b/bsp/coreip-s76-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-35 # # ----------------------------------- # RISCV_ARCH=rv64imafdc diff --git a/bsp/coreip-u54-rtl/metal-inline.h b/bsp/coreip-u54-rtl/metal-inline.h index 03d29e6..186c3ab 100644 --- a/bsp/coreip-u54-rtl/metal-inline.h +++ b/bsp/coreip-u54-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -29,6 +29,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -136,11 +137,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-u54-rtl/metal-platform.h b/bsp/coreip-u54-rtl/metal-platform.h index 562f263..8bc29b7 100644 --- a/bsp/coreip-u54-rtl/metal-platform.h +++ b/bsp/coreip-u54-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef COREIP_U54_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From cache_controller@2010000 */ #define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL #define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL diff --git a/bsp/coreip-u54-rtl/metal.default.lds b/bsp/coreip-u54-rtl/metal.default.lds index 3a5705a..7dbd4f1 100644 --- a/bsp/coreip-u54-rtl/metal.default.lds +++ b/bsp/coreip-u54-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-u54-rtl/metal.h b/bsp/coreip-u54-rtl/metal.h index 0621896..ee3c264 100644 --- a/bsp/coreip-u54-rtl/metal.h +++ b/bsp/coreip-u54-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -92,7 +92,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -191,6 +191,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -759,8 +769,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-u54-rtl/metal.ramrodata.lds b/bsp/coreip-u54-rtl/metal.ramrodata.lds index 2873493..1fd5001 100644 --- a/bsp/coreip-u54-rtl/metal.ramrodata.lds +++ b/bsp/coreip-u54-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-u54-rtl/metal.scratchpad.lds b/bsp/coreip-u54-rtl/metal.scratchpad.lds index 3a5705a..7dbd4f1 100644 --- a/bsp/coreip-u54-rtl/metal.scratchpad.lds +++ b/bsp/coreip-u54-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-u54-rtl/settings.mk b/bsp/coreip-u54-rtl/settings.mk index 6c25a1f..3815c91 100644 --- a/bsp/coreip-u54-rtl/settings.mk +++ b/bsp/coreip-u54-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 21-05-2019 10-54-35 # # ----------------------------------- # RISCV_ARCH=rv64imafdc diff --git a/bsp/coreip-u54mc-rtl/metal-inline.h b/bsp/coreip-u54mc-rtl/metal-inline.h index 58f8acc..62b9eb9 100644 --- a/bsp/coreip-u54mc-rtl/metal-inline.h +++ b/bsp/coreip-u54mc-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -29,6 +29,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -235,11 +236,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h index 6df003f..0919ca3 100644 --- a/bsp/coreip-u54mc-rtl/metal-platform.h +++ b/bsp/coreip-u54mc-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From cache_controller@2010000 */ #define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL #define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds index ea7c853..32ee163 100644 --- a/bsp/coreip-u54mc-rtl/metal.default.lds +++ b/bsp/coreip-u54mc-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h index dab7ff4..f60e70c 100644 --- a/bsp/coreip-u54mc-rtl/metal.h +++ b/bsp/coreip-u54mc-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -122,7 +122,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -293,6 +293,28 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -912,8 +934,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds index 2dca5ed..6a59904 100644 --- a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds +++ b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds index ea7c853..32ee163 100644 --- a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds +++ b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk index e59f66a..4509247 100644 --- a/bsp/coreip-u54mc-rtl/settings.mk +++ b/bsp/coreip-u54mc-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 21-05-2019 10-54-35 # # ----------------------------------- # RISCV_ARCH=rv64imac diff --git a/bsp/freedom-e310-arty/metal-inline.h b/bsp/freedom-e310-arty/metal-inline.h index b2f329f..00ce361 100644 --- a/bsp/freedom-e310-arty/metal-inline.h +++ b/bsp/freedom-e310-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/freedom-e310-arty/metal-platform.h b/bsp/freedom-e310-arty/metal-platform.h index 6ef2099..fc2a024 100644 --- a/bsp/freedom-e310-arty/metal-platform.h +++ b/bsp/freedom-e310-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef FREEDOM_E310_ARTY__METAL_PLATFORM_H diff --git a/bsp/freedom-e310-arty/metal.default.lds b/bsp/freedom-e310-arty/metal.default.lds index d331a7b..ca12e31 100644 --- a/bsp/freedom-e310-arty/metal.default.lds +++ b/bsp/freedom-e310-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/freedom-e310-arty/metal.h b/bsp/freedom-e310-arty/metal.h index 50c05a4..c6bd078 100644 --- a/bsp/freedom-e310-arty/metal.h +++ b/bsp/freedom-e310-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -212,6 +212,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/freedom-e310-arty/metal.ramrodata.lds b/bsp/freedom-e310-arty/metal.ramrodata.lds index ee6ae00..f430861 100644 --- a/bsp/freedom-e310-arty/metal.ramrodata.lds +++ b/bsp/freedom-e310-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/freedom-e310-arty/metal.scratchpad.lds b/bsp/freedom-e310-arty/metal.scratchpad.lds index 5a6d82d..cb5ed4d 100644 --- a/bsp/freedom-e310-arty/metal.scratchpad.lds +++ b/bsp/freedom-e310-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/freedom-e310-arty/settings.mk b/bsp/freedom-e310-arty/settings.mk index 6307e3a..947b357 100644 --- a/bsp/freedom-e310-arty/settings.mk +++ b/bsp/freedom-e310-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 21-05-2019 10-54-35 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/sifive-hifive-unleashed/metal-inline.h b/bsp/sifive-hifive-unleashed/metal-inline.h index 6968bab..6099519 100644 --- a/bsp/sifive-hifive-unleashed/metal-inline.h +++ b/bsp/sifive-hifive-unleashed/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -33,6 +33,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -295,11 +296,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From gpio@10060000 */ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000 = { .gpio.vtable = &__metal_driver_vtable_sifive_gpio0.gpio, diff --git a/bsp/sifive-hifive-unleashed/metal-platform.h b/bsp/sifive-hifive-unleashed/metal-platform.h index 0a1d909..19119c4 100644 --- a/bsp/sifive-hifive-unleashed/metal-platform.h +++ b/bsp/sifive-hifive-unleashed/metal-platform.h @@ -1,17 +1,20 @@ +/* Copyright 2019 SiFive, Inc */ +/* SPDX-License-Identifier: Apache-2.0 */ +/* ----------------------------------- */ +/* [XXXXX] 21-05-2019 10-54-35 */ +/* ----------------------------------- */ + #ifndef SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H #define SIFIVE_HIFIVE_UNLEASHED__METAL_PLATFORM_H /* From refclk */ #define METAL_FIXED_CLOCK__CLOCK_FREQUENCY 33333333UL -#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 33333333UL #define METAL_FIXED_CLOCK /* From tlclk */ #define METAL_FIXED_FACTOR_CLOCK__CLOCK_DIV 2UL -#define METAL_FIXED_FACTOR_CLOCK_0_CLOCK_DIV 2UL #define METAL_FIXED_FACTOR_CLOCK__CLOCK_MULT 1UL -#define METAL_FIXED_FACTOR_CLOCK_0_CLOCK_MULT 1UL #define METAL_FIXED_FACTOR_CLOCK @@ -43,12 +46,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL -#define METAL_RISCV_PMP_0_NUM_REGIONS 1UL - -#define METAL_RISCV_PMP - /* From cache_controller@2010000 */ #define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL #define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL diff --git a/bsp/sifive-hifive-unleashed/metal.default.lds b/bsp/sifive-hifive-unleashed/metal.default.lds index b4c68be..a0d0420 100644 --- a/bsp/sifive-hifive-unleashed/metal.default.lds +++ b/bsp/sifive-hifive-unleashed/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/sifive-hifive-unleashed/metal.h b/bsp/sifive-hifive-unleashed/metal.h index e72a3db..f74e931 100644 --- a/bsp/sifive-hifive-unleashed/metal.h +++ b/bsp/sifive-hifive-unleashed/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -141,7 +141,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From gpio@10060000 */ struct __metal_driver_sifive_gpio0 __metal_dt_gpio_10060000; @@ -362,6 +362,28 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -777,8 +799,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) #define __MEE_DT_MAX_GPIOS 1 diff --git a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds index 3301bb0..f0f2a6d 100644 --- a/bsp/sifive-hifive-unleashed/metal.ramrodata.lds +++ b/bsp/sifive-hifive-unleashed/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds index cf43226..dd35e29 100644 --- a/bsp/sifive-hifive-unleashed/metal.scratchpad.lds +++ b/bsp/sifive-hifive-unleashed/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/sifive-hifive1-revb/metal-inline.h b/bsp/sifive-hifive1-revb/metal-inline.h index f159c90..2d29620 100644 --- a/bsp/sifive-hifive1-revb/metal-inline.h +++ b/bsp/sifive-hifive1-revb/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -188,11 +189,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, diff --git a/bsp/sifive-hifive1-revb/metal-platform.h b/bsp/sifive-hifive1-revb/metal-platform.h index 1353847..d437f68 100644 --- a/bsp/sifive-hifive1-revb/metal-platform.h +++ b/bsp/sifive-hifive1-revb/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef SIFIVE_HIFIVE1_REVB__METAL_PLATFORM_H @@ -46,11 +46,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From aon@10000000 */ #define METAL_SIFIVE_AON0_10000000_BASE_ADDRESS 268435456UL #define METAL_SIFIVE_AON0_0_BASE_ADDRESS 268435456UL diff --git a/bsp/sifive-hifive1-revb/metal.default.lds b/bsp/sifive-hifive1-revb/metal.default.lds index 972ba9c..0a81a8e 100644 --- a/bsp/sifive-hifive1-revb/metal.default.lds +++ b/bsp/sifive-hifive1-revb/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/sifive-hifive1-revb/metal.h b/bsp/sifive-hifive1-revb/metal.h index baf508e..7ca6cdc 100644 --- a/bsp/sifive-hifive1-revb/metal.h +++ b/bsp/sifive-hifive1-revb/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -111,7 +111,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From local_external_interrupts_0 */ struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; @@ -250,6 +250,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -804,8 +814,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From local_external_interrupts_0 */ #define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) diff --git a/bsp/sifive-hifive1-revb/metal.ramrodata.lds b/bsp/sifive-hifive1-revb/metal.ramrodata.lds index 558b219..cadc499 100644 --- a/bsp/sifive-hifive1-revb/metal.ramrodata.lds +++ b/bsp/sifive-hifive1-revb/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/sifive-hifive1-revb/metal.scratchpad.lds b/bsp/sifive-hifive1-revb/metal.scratchpad.lds index 05948a2..baa38d9 100644 --- a/bsp/sifive-hifive1-revb/metal.scratchpad.lds +++ b/bsp/sifive-hifive1-revb/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/sifive-hifive1-revb/settings.mk b/bsp/sifive-hifive1-revb/settings.mk index 442f2d3..a315dab 100644 --- a/bsp/sifive-hifive1-revb/settings.mk +++ b/bsp/sifive-hifive1-revb/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 21-05-2019 10-54-35 # # ----------------------------------- # RISCV_ARCH=rv32imac diff --git a/bsp/sifive-hifive1/metal-inline.h b/bsp/sifive-hifive1/metal-inline.h index 117bff9..ef68bb7 100644 --- a/bsp/sifive-hifive1/metal-inline.h +++ b/bsp/sifive-hifive1/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/sifive-hifive1/metal-platform.h b/bsp/sifive-hifive1/metal-platform.h index f63b445..c2c508c 100644 --- a/bsp/sifive-hifive1/metal-platform.h +++ b/bsp/sifive-hifive1/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef SIFIVE_HIFIVE1__METAL_PLATFORM_H diff --git a/bsp/sifive-hifive1/metal.default.lds b/bsp/sifive-hifive1/metal.default.lds index 7346fd0..d4dabc1 100644 --- a/bsp/sifive-hifive1/metal.default.lds +++ b/bsp/sifive-hifive1/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/sifive-hifive1/metal.h b/bsp/sifive-hifive1/metal.h index 39d733d..96707bd 100644 --- a/bsp/sifive-hifive1/metal.h +++ b/bsp/sifive-hifive1/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -248,6 +248,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ diff --git a/bsp/sifive-hifive1/metal.ramrodata.lds b/bsp/sifive-hifive1/metal.ramrodata.lds index 00bc224..a79888d 100644 --- a/bsp/sifive-hifive1/metal.ramrodata.lds +++ b/bsp/sifive-hifive1/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/sifive-hifive1/metal.scratchpad.lds b/bsp/sifive-hifive1/metal.scratchpad.lds index 7a716d7..5dd7707 100644 --- a/bsp/sifive-hifive1/metal.scratchpad.lds +++ b/bsp/sifive-hifive1/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/sifive-hifive1/settings.mk b/bsp/sifive-hifive1/settings.mk index ed70259..966f928 100644 --- a/bsp/sifive-hifive1/settings.mk +++ b/bsp/sifive-hifive1/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 21-05-2019 10-54-35 # # ----------------------------------- # RISCV_ARCH=rv32imac -- cgit v1.2.3