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/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "SiFive,FE200G-dev", "fe200-dev", "sifive-dev";
model = "SiFive,FE200G";
L10: cpus {
#address-cells = <1>;
#size-cells = <0>;
L3: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,caboose0", "riscv";
device_type = "cpu";
reg = <0x0>;
riscv,isa = "rv32imc";
status = "okay";
timebase-frequency = <1000000>;
hardware-exec-breakpoint-count = <4>;
L2: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L9: soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "SiFive,FE200G-soc", "fe200-soc", "sifive-soc", "simple-bus";
ranges;
L7: ahb-sys-port@20000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sifive,ahb-sys-port", "sifive,ahb-port", "sifive,sys-port", "simple-bus";
ranges = <0x20000000 0x20000000 0x20000000>;
};
L1: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
interrupts-extended = <&L2 65535>;
reg = <0x0 0x1000>;
reg-names = "control";
};
L0: interrupt-controller@2000000 {
#interrupt-cells = <1>;
compatible = "sifive,clic0";
interrupt-controller;
interrupts-extended = <&L2 3 &L2 7 &L2 11>;
reg = <0x2000000 0x1000000>;
reg-names = "control";
sifive,numints = <48>;
sifive,numlevels = <16>;
sifive,numintbits = <2>;
};
L6: local-external-interrupts-0 {
compatible = "sifive,local-external-interrupts0";
interrupt-parent = <&L0>;
interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
};
L4: teststatus@4000 {
compatible = "sifive,test0";
reg = <0x4000 0x1000>;
reg-names = "control";
};
test_memory: testram@20000000 {
compatible = "sifive,testram0";
reg = <0x20000000 0x8000000>;
reg-names = "mem";
word-size-bytes = <4>;
};
};
};
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