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/dts-v1/;
/ {
#address-cells = <2>;
#size-cells = <2>;
compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev";
model = "SiFive,FU540G";
L19: cpus {
#address-cells = <1>;
#size-cells = <0>;
L8: cpu@0 {
clock-frequency = <0>;
compatible = "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
d-cache-size = <16384>;
d-tlb-sets = <1>;
d-tlb-size = <32>;
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <64>;
i-cache-size = <16384>;
i-tlb-sets = <1>;
i-tlb-size = <32>;
mmu-type = "riscv,sv39";
next-level-cache = <&L16>;
reg = <0x0>;
riscv,isa = "rv64imafdc";
sifive,itim = <&L6>;
status = "okay";
timebase-frequency = <1000000>;
tlb-split;
L5: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
L11: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x20000000>;
};
L18: soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus";
ranges;
L13: axi4-periph-port@20000000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "sifive,axi4-periph-port", "sifive,axi4-port", "sifive,periph-port", "simple-bus";
ranges = <0x0 0x20000000 0x0 0x20000000 0x0 0x20000000 0x1 0x0 0x1 0x0 0xf 0x0>;
};
L12: axi4-sys-port@40000000 {
#address-cells = <2>;
#size-cells = <2>;
compatible = "sifive,axi4-sys-port", "sifive,axi4-port", "sifive,sys-port", "simple-bus";
ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000 0x10 0x0 0x10 0x0 0x30 0x0>;
};
L7: bus-error-unit@1700000 {
compatible = "sifive,buserror0";
interrupt-parent = <&L2>;
interrupts = <132>;
reg = <0x0 0x1700000 0x0 0x1000>;
reg-names = "control";
};
L16: cache-controller@2010000 {
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <512>;
cache-size = <262144>;
cache-unified;
compatible = "sifive,ccache0", "cache";
interrupt-parent = <&L2>;
interrupts = <128 129 130 131>;
next-level-cache = <&L0 &L11>;
reg = <0x0 0x2010000 0x0 0x1000 0x0 0x8000000 0x0 0x40000>;
reg-names = "control", "sideband";
sifive,ecc-granularity = <8>;
sifive,mshr-count = <5>;
};
L3: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&L5 3 &L5 7>;
reg = <0x0 0x2000000 0x0 0x10000>;
reg-names = "control";
};
L4: debug-controller@0 {
compatible = "sifive,debug-013", "riscv,debug-013";
interrupts-extended = <&L5 65535>;
reg = <0x0 0x0 0x0 0x1000>;
reg-names = "control";
};
L1: error-device@3000 {
compatible = "sifive,error0";
reg = <0x0 0x3000 0x0 0x1000>;
};
L10: global-external-interrupts {
interrupt-parent = <&L2>;
interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>;
};
L2: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&L5 11 &L5 9>;
reg = <0x0 0xc000000 0x0 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <132>;
};
L6: itim@1800000 {
compatible = "sifive,itim0";
reg = <0x0 0x1800000 0x0 0x4000>;
reg-names = "mem";
};
L0: rom@a000000 {
compatible = "ucbbar,cacheable-zero0";
reg = <0x0 0xa000000 0x0 0x2000000>;
};
L9: teststatus@4000 {
compatible = "sifive,test0";
reg = <0x0 0x4000 0x0 0x1000>;
reg-names = "control";
};
};
};
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