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/dts-v1/;
/ {
#address-cells = <1>;
#size-cells = <1>;
compatible = "sifive,freedom-e310-arty";
model = "sifive,freedom-e310-arty";
chosen {
stdout-path = "/soc/serial@10013000:115200";
mee,entry = <&sip0 0x400000>;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
compatible = "sifive,fe310-g000";
L6: cpu@0 {
clocks = <&hfclk>;
compatible = "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
i-cache-sets = <128>;
i-cache-size = <16384>;
next-level-cache = <&sip0>;
reg = <0>;
riscv,isa = "rv32imac";
sifive,dtim = <&dtim>;
sifive,itim = <&itim>;
status = "okay";
timebase-frequency = <1000000>;
hlic: interrupt-controller {
#interrupt-cells = <1>;
compatible = "riscv,cpu-intc";
interrupt-controller;
};
};
};
soc {
#address-cells = <1>;
#size-cells = <1>;
#clock-cells = <1>;
compatible = "sifive,freedom-e310-arty";
ranges;
hfclk: clock@0 {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <65000000>;
};
clint: clint@2000000 {
compatible = "riscv,clint0";
interrupts-extended = <&hlic 3 &hlic 7>;
reg = <0x2000000 0x10000>;
reg-names = "control";
};
local-external-interrupts-0 {
compatible = "sifive,local-external-interrupts0";
interrupt-parent = <&hlic>;
interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
};
plic: interrupt-controller@c000000 {
#interrupt-cells = <1>;
compatible = "riscv,plic0";
interrupt-controller;
interrupts-extended = <&hlic 11>;
reg = <0xc000000 0x4000000>;
reg-names = "control";
riscv,max-priority = <7>;
riscv,ndev = <26>;
};
global-external-interrupts {
compatile = "sifive,global-external-interrupts0";
interrupt-parent = <&plic>;
interrupts = <1 2 3 4>;
};
debug-controller@0 {
compatible = "sifive,debug-011", "riscv,debug-011";
interrupts-extended = <&hlic 65535>;
reg = <0x0 0x100>;
reg-names = "control";
};
maskrom@1000 {
reg = <0x1000 0x2000>;
reg-names = "mem";
};
otp@20000 {
reg = <0x20000 0x2000 0x10010000 0x1000>;
reg-names = "mem", "control";
};
dtim: dtim@80000000 {
compatible = "sifive,dtim0";
reg = <0x80000000 0x4000>;
reg-names = "mem";
};
itim: itim@8000000 {
compatible = "sifive,itim0";
reg = <0x8000000 0x4000>;
reg-names = "mem";
};
pwm@10015000 {
compatible = "sifive,pwm0";
interrupt-parent = <&plic>;
interrupts = <23 24 25 26>;
reg = <0x10015000 0x1000>;
reg-names = "control";
};
gpio0: gpio@10012000 {
compatible = "sifive,gpio0";
interrupt-parent = <&plic>;
interrupts = <7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22>;
reg = <0x10012000 0x1000>;
reg-names = "control";
};
uart0: serial@10013000 {
compatible = "sifive,uart0";
interrupt-parent = <&plic>;
interrupts = <5>;
reg = <0x10013000 0x1000>;
reg-names = "control";
clocks = <&hfclk>;
pinmux = <&gpio0 0x30000 0x30000>;
};
sip0: spi@10014000 {
compatible = "sifive,spi0";
interrupt-parent = <&plic>;
interrupts = <6>;
reg = <0x10014000 0x1000 0x20000000 0x20000000>;
reg-names = "control", "mem";
};
};
};
|
