blob: eaa722eb3412111b14e61c278a6655b2d772befe (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
|
/* Copyright 2019 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
/* ----------------------------------- */
/* [XXXXX] 28-05-2019 10-06-17 */
/* ----------------------------------- */
#ifndef SIFIVE_HIFIVE1__METAL_PLATFORM_H
#define SIFIVE_HIFIVE1__METAL_PLATFORM_H
/* From clock@0 */
#define METAL_FIXED_CLOCK_0_CLOCK_FREQUENCY 16000000UL
/* From clock@2 */
#define METAL_FIXED_CLOCK_2_CLOCK_FREQUENCY 72000000UL
/* From clock@5 */
#define METAL_FIXED_CLOCK_5_CLOCK_FREQUENCY 32000000UL
#define METAL_FIXED_CLOCK
/* From clint@2000000 */
#define METAL_RISCV_CLINT0_2000000_BASE_ADDRESS 33554432UL
#define METAL_RISCV_CLINT0_0_BASE_ADDRESS 33554432UL
#define METAL_RISCV_CLINT0_2000000_SIZE 65536UL
#define METAL_RISCV_CLINT0_0_SIZE 65536UL
#define METAL_RISCV_CLINT0
#define METAL_RISCV_CLINT0_MSIP_BASE 0UL
#define METAL_RISCV_CLINT0_MTIMECMP_BASE 16384UL
#define METAL_RISCV_CLINT0_MTIME 49144UL
/* From interrupt_controller@c000000 */
#define METAL_RISCV_PLIC0_C000000_BASE_ADDRESS 201326592UL
#define METAL_RISCV_PLIC0_0_BASE_ADDRESS 201326592UL
#define METAL_RISCV_PLIC0_C000000_SIZE 67108864UL
#define METAL_RISCV_PLIC0_0_SIZE 67108864UL
#define METAL_RISCV_PLIC0_C000000_RISCV_MAX_PRIORITY 7UL
#define METAL_RISCV_PLIC0_0_RISCV_MAX_PRIORITY 7UL
#define METAL_RISCV_PLIC0_C000000_RISCV_NDEV 27UL
#define METAL_RISCV_PLIC0_0_RISCV_NDEV 27UL
#define METAL_RISCV_PLIC0
#define METAL_RISCV_PLIC0_PRIORITY_BASE 0UL
#define METAL_RISCV_PLIC0_PENDING_BASE 4096UL
#define METAL_RISCV_PLIC0_ENABLE_BASE 8192UL
#define METAL_RISCV_PLIC0_THRESHOLD 2097152UL
#define METAL_RISCV_PLIC0_CLAIM 2097156UL
/* From aon@10000000 */
#define METAL_SIFIVE_AON0_10000000_BASE_ADDRESS 268435456UL
#define METAL_SIFIVE_AON0_0_BASE_ADDRESS 268435456UL
#define METAL_SIFIVE_AON0_10000000_SIZE 32768UL
#define METAL_SIFIVE_AON0_0_SIZE 32768UL
#define METAL_SIFIVE_AON0
#define METAL_SIFIVE_AON0_WDOGCFG 0UL
#define METAL_SIFIVE_AON0_WDOGCOUNT 8UL
#define METAL_SIFIVE_AON0_WDOGS 16UL
#define METAL_SIFIVE_AON0_WDOGFEED 24UL
#define METAL_SIFIVE_AON0_WDOGKEY 28UL
#define METAL_SIFIVE_AON0_WDOGCMP 32UL
#define METAL_SIFIVE_AON0_RTCCFG 64UL
#define METAL_SIFIVE_AON0_RTCLO 72UL
#define METAL_SIFIVE_AON0_RTCHI 72UL
#define METAL_SIFIVE_AON0_RTCS 80UL
#define METAL_SIFIVE_AON0_RTCCMP 96UL
#define METAL_SIFIVE_AON0_LFROSCCFG 112UL
#define METAL_SIFIVE_AON0_BACKUP0 128UL
#define METAL_SIFIVE_AON0_BACKUP1 132UL
#define METAL_SIFIVE_AON0_BACKUP2 136UL
#define METAL_SIFIVE_AON0_BACKUP3 140UL
#define METAL_SIFIVE_AON0_BACKUP4 144UL
#define METAL_SIFIVE_AON0_BACKUP5 148UL
#define METAL_SIFIVE_AON0_BACKUP6 152UL
#define METAL_SIFIVE_AON0_BACKUP7 152UL
#define METAL_SIFIVE_AON0_BACKUP8 160UL
#define METAL_SIFIVE_AON0_BACKUP9 164UL
#define METAL_SIFIVE_AON0_BACKUP10 168UL
#define METAL_SIFIVE_AON0_BACKUP11 172UL
#define METAL_SIFIVE_AON0_BACKUP12 176UL
#define METAL_SIFIVE_AON0_BACKUP13 180UL
#define METAL_SIFIVE_AON0_BACKUP14 184UL
#define METAL_SIFIVE_AON0_BACKUP15 188UL
#define METAL_SIFIVE_AON0_BACKUP16 192UL
#define METAL_SIFIVE_AON0_BACKUP17 196UL
#define METAL_SIFIVE_AON0_BACKUP18 200UL
#define METAL_SIFIVE_AON0_BACKUP19 204UL
#define METAL_SIFIVE_AON0_BACKUP20 208UL
#define METAL_SIFIVE_AON0_BACKUP21 212UL
#define METAL_SIFIVE_AON0_BACKUP22 216UL
#define METAL_SIFIVE_AON0_BACKUP23 220UL
#define METAL_SIFIVE_AON0_BACKUP24 224UL
#define METAL_SIFIVE_AON0_BACKUP25 228UL
#define METAL_SIFIVE_AON0_BACKUP26 232UL
#define METAL_SIFIVE_AON0_BACKUP27 236UL
#define METAL_SIFIVE_AON0_BACKUP28 240UL
#define METAL_SIFIVE_AON0_BACKUP29 244UL
#define METAL_SIFIVE_AON0_BACKUP30 248UL
#define METAL_SIFIVE_AON0_BACKUP31 252UL
#define METAL_SIFIVE_AON0_PMU_WAKEUP_BASE 256UL
#define METAL_SIFIVE_AON0_PWM_SLEEP_BASE 288UL
#define METAL_SIFIVE_AON0_PMUIE 320UL
#define METAL_SIFIVE_AON0_PMUCAUSE 324UL
#define METAL_SIFIVE_AON0_PMUSLEEP 328UL
#define METAL_SIFIVE_AON0_PMUKEY 332UL
/* From clock@3 */
#define METAL_SIFIVE_FE310_G000_HFROSC
/* From clock@1 */
#define METAL_SIFIVE_FE310_G000_HFXOSC
/* From prci@10008000 */
#define METAL_SIFIVE_FE310_G000_PRCI_10008000_BASE_ADDRESS 268468224UL
#define METAL_SIFIVE_FE310_G000_PRCI_0_BASE_ADDRESS 268468224UL
#define METAL_SIFIVE_FE310_G000_PRCI_10008000_SIZE 32768UL
#define METAL_SIFIVE_FE310_G000_PRCI_0_SIZE 32768UL
#define METAL_SIFIVE_FE310_G000_PRCI
#define METAL_SIFIVE_FE310_G000_PRCI_HFROSCCFG 0UL
#define METAL_SIFIVE_FE310_G000_PRCI_HFXOSCCFG 4UL
#define METAL_SIFIVE_FE310_G000_PRCI_PLLCFG 8UL
#define METAL_SIFIVE_FE310_G000_PRCI_PLLOUTDIV 12UL
/* From clock@4 */
#define METAL_SIFIVE_FE310_G000_PLL_4_CLOCK_FREQUENCY 16000000UL
#define METAL_SIFIVE_FE310_G000_PLL
/* From gpio@10012000 */
#define METAL_SIFIVE_GPIO0_10012000_BASE_ADDRESS 268509184UL
#define METAL_SIFIVE_GPIO0_0_BASE_ADDRESS 268509184UL
#define METAL_SIFIVE_GPIO0_10012000_SIZE 4096UL
#define METAL_SIFIVE_GPIO0_0_SIZE 4096UL
#define METAL_SIFIVE_GPIO0
#define METAL_SIFIVE_GPIO0_VALUE 0UL
#define METAL_SIFIVE_GPIO0_INPUT_EN 4UL
#define METAL_SIFIVE_GPIO0_OUTPUT_EN 8UL
#define METAL_SIFIVE_GPIO0_PORT 12UL
#define METAL_SIFIVE_GPIO0_PUE 16UL
#define METAL_SIFIVE_GPIO0_DS 20UL
#define METAL_SIFIVE_GPIO0_RISE_IE 24UL
#define METAL_SIFIVE_GPIO0_RISE_IP 28UL
#define METAL_SIFIVE_GPIO0_FALL_IE 32UL
#define METAL_SIFIVE_GPIO0_FALL_IP 36UL
#define METAL_SIFIVE_GPIO0_HIGH_IE 40UL
#define METAL_SIFIVE_GPIO0_HIGH_IP 44UL
#define METAL_SIFIVE_GPIO0_LOW_IE 48UL
#define METAL_SIFIVE_GPIO0_LOW_IP 52UL
#define METAL_SIFIVE_GPIO0_IOF_EN 56UL
#define METAL_SIFIVE_GPIO0_IOF_SEL 60UL
#define METAL_SIFIVE_GPIO0_OUT_XOR 64UL
/* From led@0red */
/* From led@0green */
/* From led@0blue */
#define METAL_SIFIVE_GPIO_LEDS
/* From local_external_interrupts_0 */
#define METAL_SIFIVE_LOCAL_EXTERNAL_INTERRUPTS0
/* From pwm@10015000 */
#define METAL_SIFIVE_PWM0_10015000_BASE_ADDRESS 268521472UL
#define METAL_SIFIVE_PWM0_0_BASE_ADDRESS 268521472UL
#define METAL_SIFIVE_PWM0_10015000_SIZE 4096UL
#define METAL_SIFIVE_PWM0_0_SIZE 4096UL
#define METAL_SIFIVE_PWM0
#define METAL_SIFIVE_PWM0_PWMCFG 0UL
#define METAL_SIFIVE_PWM0_PWMCOUNT 8UL
#define METAL_SIFIVE_PWM0_PWMS 16UL
#define METAL_SIFIVE_PWM0_PWMCMP0 32UL
#define METAL_SIFIVE_PWM0_PWMCMP1 36UL
#define METAL_SIFIVE_PWM0_PWMCMP2 40UL
#define METAL_SIFIVE_PWM0_PWMCMP3 44UL
/* From spi@10014000 */
#define METAL_SIFIVE_SPI0_10014000_BASE_ADDRESS 268517376UL
#define METAL_SIFIVE_SPI0_0_BASE_ADDRESS 268517376UL
#define METAL_SIFIVE_SPI0_10014000_SIZE 4096UL
#define METAL_SIFIVE_SPI0_0_SIZE 4096UL
#define METAL_SIFIVE_SPI0
#define METAL_SIFIVE_SPI0_SCKDIV 0UL
#define METAL_SIFIVE_SPI0_SCKMODE 4UL
#define METAL_SIFIVE_SPI0_CSID 16UL
#define METAL_SIFIVE_SPI0_CSDEF 20UL
#define METAL_SIFIVE_SPI0_CSMODE 24UL
#define METAL_SIFIVE_SPI0_DELAY0 40UL
#define METAL_SIFIVE_SPI0_DELAY1 44UL
#define METAL_SIFIVE_SPI0_FMT 64UL
#define METAL_SIFIVE_SPI0_TXDATA 72UL
#define METAL_SIFIVE_SPI0_RXDATA 76UL
#define METAL_SIFIVE_SPI0_TXMARK 80UL
#define METAL_SIFIVE_SPI0_RXMARK 84UL
#define METAL_SIFIVE_SPI0_FCTRL 96UL
#define METAL_SIFIVE_SPI0_FFMT 100UL
#define METAL_SIFIVE_SPI0_IE 112UL
#define METAL_SIFIVE_SPI0_IP 116UL
/* From serial@10013000 */
#define METAL_SIFIVE_UART0_10013000_BASE_ADDRESS 268513280UL
#define METAL_SIFIVE_UART0_0_BASE_ADDRESS 268513280UL
#define METAL_SIFIVE_UART0_10013000_SIZE 4096UL
#define METAL_SIFIVE_UART0_0_SIZE 4096UL
#define METAL_SIFIVE_UART0
#define METAL_SIFIVE_UART0_TXDATA 0UL
#define METAL_SIFIVE_UART0_RXDATA 4UL
#define METAL_SIFIVE_UART0_TXCTRL 8UL
#define METAL_SIFIVE_UART0_RXCTRL 12UL
#define METAL_SIFIVE_UART0_IE 16UL
#define METAL_SIFIVE_UART0_IP 20UL
#define METAL_SIFIVE_UART0_DIV 24UL
#endif /* SIFIVE_HIFIVE1__METAL_PLATFORM_H*/
|
