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authorBunnaroath Sou <bsou@sifive.com>2019-03-26 12:07:46 -0700
committerBunnaroath Sou <bsou@sifive.com>2019-03-26 15:13:59 -0700
commit96f7c530cc7ec894ed8c326a47dc496fb7b9c35f (patch)
tree34721983e5e3b6b579f5bee8b0c0ab790f9a5538
parentedd89ecddd9abea9fa47b91487bf6bb8360b1c66 (diff)
Making dhrystone public
-rw-r--r--.gitmodules3
-rw-r--r--bsp/coreip-e31-arty/settings.mk2
-rw-r--r--bsp/coreip-e31-rtl/settings.mk2
m---------software/dhrystone0
4 files changed, 5 insertions, 2 deletions
diff --git a/.gitmodules b/.gitmodules
index bd6e9c4..5c6f9e1 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -40,3 +40,6 @@
[submodule "software/sifive-welcome"]
path = software/sifive-welcome
url = https://github.com/sifive/sifive-welcome
+[submodule "software/dhrystone"]
+ path = software/dhrystone
+ url = https://github.com/sifive/benchmark-dhrystone
diff --git a/bsp/coreip-e31-arty/settings.mk b/bsp/coreip-e31-arty/settings.mk
index 0b9c2cb..c2a2547 100644
--- a/bsp/coreip-e31-arty/settings.mk
+++ b/bsp/coreip-e31-arty/settings.mk
@@ -1,5 +1,5 @@
RISCV_ARCH=rv32imac
RISCV_ABI=ilp32
-RISCV_CMODEL=medlow
+RISCV_CMODEL=medany
TARGET_TAGS=fpga openocd
diff --git a/bsp/coreip-e31-rtl/settings.mk b/bsp/coreip-e31-rtl/settings.mk
index f60f250..50ec3c7 100644
--- a/bsp/coreip-e31-rtl/settings.mk
+++ b/bsp/coreip-e31-rtl/settings.mk
@@ -1,6 +1,6 @@
RISCV_ARCH=rv32imac
RISCV_ABI=ilp32
-RISCV_CMODEL=medlow
+RISCV_CMODEL=medany
COREIP_MEM_WIDTH=32
diff --git a/software/dhrystone b/software/dhrystone
new file mode 160000
+Subproject 1472b5092fa52551670908aa15d48eb974ccd45