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authorBunnaroath Sou <35707615+bsousi5@users.noreply.github.com>2019-03-01 10:05:34 -0800
committerGitHub <noreply@github.com>2019-03-01 10:05:34 -0800
commitfb3cddda6c0342ae6c91918e769eecafbabb55b0 (patch)
treeee323a74e2355cfedd0d528a407a6d5d252e8a7c /bsp/coreip-e20
parentbbea559f684a5eee7df45429ed55d41330f44474 (diff)
parentcbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 (diff)
Merge pull request #183 from sifive/e-series
Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty
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+The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines.
+
+This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
+
+- 1 hart with RV32IMC core
+- 4 hardware breakpoints