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| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-03-01 10:05:34 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-01 10:05:34 -0800 |
| commit | fb3cddda6c0342ae6c91918e769eecafbabb55b0 (patch) | |
| tree | ee323a74e2355cfedd0d528a407a6d5d252e8a7c /bsp/coreip-e20 | |
| parent | bbea559f684a5eee7df45429ed55d41330f44474 (diff) | |
| parent | cbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 (diff) | |
Merge pull request #183 from sifive/e-series
Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty
Diffstat (limited to 'bsp/coreip-e20')
| -rw-r--r-- | bsp/coreip-e20/README.md | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/bsp/coreip-e20/README.md b/bsp/coreip-e20/README.md new file mode 100644 index 0000000..f908327 --- /dev/null +++ b/bsp/coreip-e20/README.md @@ -0,0 +1,6 @@ +The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMC core +- 4 hardware breakpoints |