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| author | Bunnaroath Sou <bsou@sifive.com> | 2019-02-25 18:57:35 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-02-25 18:57:35 -0800 |
| commit | e18401806b38ca0f60394780191df4b72cb2f88a (patch) | |
| tree | 50c31a3efbe1f1acce3aeec706c0d8d1227c0964 /bsp/coreip-e21 | |
| parent | bbea559f684a5eee7df45429ed55d41330f44474 (diff) | |
Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty
Diffstat (limited to 'bsp/coreip-e21')
| -rw-r--r-- | bsp/coreip-e21/README.md | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/bsp/coreip-e21/README.md b/bsp/coreip-e21/README.md new file mode 100644 index 0000000..31719b3 --- /dev/null +++ b/bsp/coreip-e21/README.md @@ -0,0 +1,6 @@ +The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 4 regions |