diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-21 10:51:18 -0700 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-21 10:54:29 -0700 |
| commit | b87018b8a5afa98a6f799527d9a4417290349a4a (patch) | |
| tree | bfd29bb74aeade1c864ef431691b86e2ea0ab442 /bsp/coreip-e24-arty | |
| parent | 1054095bdf4d5a989ed1267051cc6fd6eefc2fcd (diff) | |
Modify BSP DTSs to use riscv,pmpregions property
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-e24-arty')
| -rw-r--r-- | bsp/coreip-e24-arty/design.dts | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/bsp/coreip-e24-arty/design.dts b/bsp/coreip-e24-arty/design.dts index f288b54..ba6b037 100644 --- a/bsp/coreip-e24-arty/design.dts +++ b/bsp/coreip-e24-arty/design.dts @@ -21,6 +21,7 @@ device_type = "cpu"; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <4>; status = "okay"; timebase-frequency = <32000000>; hardware-exec-breakpoint-count = <4>; @@ -36,10 +37,6 @@ #size-cells = <1>; compatible = "SiFive,FE240G-soc", "fe240-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <4>; - }; hfclk: clock@0 { #clock-cells = <0>; compatible = "fixed-clock"; |