diff options
| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-03-05 15:46:02 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-05 15:46:02 -0800 |
| commit | ca5a57b10b446871d584e590bfa689c39b1d5e8c (patch) | |
| tree | 18c33aec326bdc274f804512bed600ec5924dddd /bsp/coreip-e24-arty | |
| parent | 3e51e0289ec728b6ff6dcf90bb8ddcb50c24cb04 (diff) | |
| parent | 04654e6c468e853ddef3423221bbda1c8e999dd6 (diff) | |
Merge pull request #190 from sifive/coreip-19.2
Update/add E31, E34, S51, S54 arty targets for all 19.2 CoreIPs release
Diffstat (limited to 'bsp/coreip-e24-arty')
| -rw-r--r-- | bsp/coreip-e24-arty/README.md | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/bsp/coreip-e24-arty/README.md b/bsp/coreip-e24-arty/README.md new file mode 100644 index 0000000..79dfae8 --- /dev/null +++ b/bsp/coreip-e24-arty/README.md @@ -0,0 +1,13 @@ +The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA’s F standard extension. The E24’s efficiency, coupled with hardware floating-point capabilities, make it exceptional at motor control, sensor fusion, and IoT applications. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions +- Up to 153 CLIC interrupt signals that can be connected to off core complex devices, with 16 levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches |