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authorNathaniel Graff <nathaniel.graff@sifive.com>2019-03-07 22:47:38 +0000
committerGitHub <noreply@github.com>2019-03-07 22:47:38 +0000
commit2b9cbfe9011bca74aee3c1204d7db4b4236b23f0 (patch)
treefccb6fa1d7c2c065642cb21cc4d421e3ae8206eb /bsp/coreip-e24-rtl/README.md
parentc6c0fbf23d1fc8aa9b99eae19b6e3741c8d51548 (diff)
parent983a630b07f08af869adc78cb37bf634389519af (diff)
Merge pull request #197 from sifive/rename-rtl-targets
Rename coreip-X to coreip-X-rtl
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+The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA’s F standard extension. The E24’s efficiency, coupled with hardware floating-point capabilities, make it exceptional at motor control, sensor fusion, and IoT applications.
+
+This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports:
+
+- 1 hart with RV32IMAFC core
+- 4 hardware breakpoints
+- Physical Memory Protection with 4 regions
+