Delete coreip BSPs

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>

1 files changed, 0 insertions, 14 deletions

diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md
deleted file mode 100644
index c6558cb..0000000
--- a/bsp/coreip-e31-arty/README.md
+++ /dev/null
@@ -1,14 +0,0 @@
-The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications.
-
-This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports:
-
-- 1 hart with RV32IMAC core
-- 4 hardware breakpoints
-- Physical Memory Protection with 8 regions
-- 16 local interrupts signal that can be connected to off core complex devices
-- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels
-- GPIO memory with 16 interrupt lines
-- SPI memory with 1 interrupt line
-- Serial port with 1 interrupt line
-- 4 RGB LEDS
-- 4 Buttons and 4 Switches