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| author | Bunnaroath Sou <35707615+bsousi5@users.noreply.github.com> | 2019-03-05 15:46:02 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-03-05 15:46:02 -0800 |
| commit | ca5a57b10b446871d584e590bfa689c39b1d5e8c (patch) | |
| tree | 18c33aec326bdc274f804512bed600ec5924dddd /bsp/coreip-e34-arty/openocd.cfg | |
| parent | 3e51e0289ec728b6ff6dcf90bb8ddcb50c24cb04 (diff) | |
| parent | 04654e6c468e853ddef3423221bbda1c8e999dd6 (diff) | |
Merge pull request #190 from sifive/coreip-19.2
Update/add E31, E34, S51, S54 arty targets for all 19.2 CoreIPs release
Diffstat (limited to 'bsp/coreip-e34-arty/openocd.cfg')
| -rw-r--r-- | bsp/coreip-e34-arty/openocd.cfg | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/bsp/coreip-e34-arty/openocd.cfg b/bsp/coreip-e34-arty/openocd.cfg new file mode 100644 index 0000000..34b9f88 --- /dev/null +++ b/bsp/coreip-e34-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000 +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off |