Update BSPs

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>

7 files changed, 23 insertions, 18 deletions

diff --git a/bsp/coreip-e76-arty/metal-inline.h b/bsp/coreip-e76-arty/metal-inline.h
index d1af334..d1ec2ff 100644
--- a/bsp/coreip-e76-arty/metal-inline.h
+++ b/bsp/coreip-e76-arty/metal-inline.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-01        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
diff --git a/bsp/coreip-e76-arty/metal-platform.h b/bsp/coreip-e76-arty/metal-platform.h
index a08971f..237a951 100644
--- a/bsp/coreip-e76-arty/metal-platform.h
+++ b/bsp/coreip-e76-arty/metal-platform.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-01        */
 /* ----------------------------------- */
 
 #ifndef COREIP_E76_ARTY__METAL_PLATFORM_H
diff --git a/bsp/coreip-e76-arty/metal.default.lds b/bsp/coreip-e76-arty/metal.default.lds
index fc983a7..573538c 100644
--- a/bsp/coreip-e76-arty/metal.default.lds
+++ b/bsp/coreip-e76-arty/metal.default.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-01        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 1);
 
 
 	.init 		:
diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h
index 0c4f0eb..51cf900 100644
--- a/bsp/coreip-e76-arty/metal.h
+++ b/bsp/coreip-e76-arty/metal.h
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-01        */
 /* ----------------------------------- */
 
 #ifndef ASSEMBLY
@@ -75,18 +75,18 @@
 
 #include <metal/drivers/fixed-clock.h>
 #include <metal/memory.h>
-#include <metal/drivers/riscv,clint0.h>
-#include <metal/drivers/riscv,cpu.h>
-#include <metal/drivers/riscv,plic0.h>
+#include <metal/drivers/riscv_clint0.h>
+#include <metal/drivers/riscv_cpu.h>
+#include <metal/drivers/riscv_plic0.h>
 #include <metal/pmp.h>
-#include <metal/drivers/sifive,global-external-interrupts0.h>
-#include <metal/drivers/sifive,gpio0.h>
-#include <metal/drivers/sifive,gpio-buttons.h>
-#include <metal/drivers/sifive,gpio-leds.h>
-#include <metal/drivers/sifive,gpio-switches.h>
-#include <metal/drivers/sifive,spi0.h>
-#include <metal/drivers/sifive,test0.h>
-#include <metal/drivers/sifive,uart0.h>
+#include <metal/drivers/sifive_global-external-interrupts0.h>
+#include <metal/drivers/sifive_gpio0.h>
+#include <metal/drivers/sifive_gpio-buttons.h>
+#include <metal/drivers/sifive_gpio-leds.h>
+#include <metal/drivers/sifive_gpio-switches.h>
+#include <metal/drivers/sifive_spi0.h>
+#include <metal/drivers/sifive_test0.h>
+#include <metal/drivers/sifive_uart0.h>
 
 /* From tlclk */
 struct __metal_driver_fixed_clock __metal_dt_tlclk;
diff --git a/bsp/coreip-e76-arty/metal.ramrodata.lds b/bsp/coreip-e76-arty/metal.ramrodata.lds
index f53fd33..e44853a 100644
--- a/bsp/coreip-e76-arty/metal.ramrodata.lds
+++ b/bsp/coreip-e76-arty/metal.ramrodata.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-01        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 1);
 
 
 	.init 		:
diff --git a/bsp/coreip-e76-arty/metal.scratchpad.lds b/bsp/coreip-e76-arty/metal.scratchpad.lds
index eadc43f..f467347 100644
--- a/bsp/coreip-e76-arty/metal.scratchpad.lds
+++ b/bsp/coreip-e76-arty/metal.scratchpad.lds
@@ -1,7 +1,7 @@
 /* Copyright 2019 SiFive, Inc */
 /* SPDX-License-Identifier: Apache-2.0 */
 /* ----------------------------------- */
-/* [XXXXX] 23-05-2019 13-29-49        */
+/* [XXXXX] 28-05-2019 10-06-01        */
 /* ----------------------------------- */
 
 OUTPUT_ARCH("riscv")
@@ -29,6 +29,7 @@ SECTIONS
 	PROVIDE(__stack_size = __stack_size);
 	__heap_size = DEFINED(__heap_size) ? __heap_size : 0x400;
 	PROVIDE(__metal_boot_hart = 0);
+	PROVIDE(__metal_chicken_bit = 1);
 
 
 	.init 		:
diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk
index 1e501a6..87b6174 100644
--- a/bsp/coreip-e76-arty/settings.mk
+++ b/bsp/coreip-e76-arty/settings.mk
@@ -1,12 +1,14 @@
 # Copyright 2019 SiFive, Inc #
 # SPDX-License-Identifier: Apache-2.0 #
 # ----------------------------------- #
-# [XXXXX] 23-05-2019 13-29-49        #
+# [XXXXX] 28-05-2019 10-06-01        #
 # ----------------------------------- #
 
 RISCV_ARCH=rv32imafc
 RISCV_ABI=ilp32f
 RISCV_CMODEL=medlow
+RISCV_SERIES=sifive-7-series
 
 TARGET_TAGS=fpga openocd
 TARGET_DHRY_ITERS=20000000
+TARGET_CORE_ITERS=5000