diff options
author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-21 10:51:18 -0700 |
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committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-05-21 10:54:29 -0700 |
commit | b87018b8a5afa98a6f799527d9a4417290349a4a (patch) | |
tree | bfd29bb74aeade1c864ef431691b86e2ea0ab442 /bsp/coreip-s51-rtl | |
parent | 1054095bdf4d5a989ed1267051cc6fd6eefc2fcd (diff) |
Modify BSP DTSs to use riscv,pmpregions property
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/coreip-s51-rtl')
-rw-r--r-- | bsp/coreip-s51-rtl/design.dts | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/bsp/coreip-s51-rtl/design.dts b/bsp/coreip-s51-rtl/design.dts index bbbab4d..3a7bf54 100644 --- a/bsp/coreip-s51-rtl/design.dts +++ b/bsp/coreip-s51-rtl/design.dts @@ -17,6 +17,7 @@ i-cache-size = <16384>; reg = <0x0>; riscv,isa = "rv64imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; @@ -34,10 +35,6 @@ #size-cells = <2>; compatible = "SiFive,FS510G-soc", "fs510-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L12: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; |