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| author | Bunnaroath Sou <bsou@sifive.com> | 2019-02-27 15:46:57 -0800 |
|---|---|---|
| committer | Bunnaroath Sou <bsou@sifive.com> | 2019-02-27 15:46:57 -0800 |
| commit | cbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 (patch) | |
| tree | ee323a74e2355cfedd0d528a407a6d5d252e8a7c /bsp/coreip-s51 | |
| parent | 7570a33f98d1980b9bc9e799b0b202fde2cda1ce (diff) | |
Spellcheck correction readme for bsp targets for E20, E21, E31/Arty, S51/Arty
Diffstat (limited to 'bsp/coreip-s51')
| -rw-r--r-- | bsp/coreip-s51/README.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md index a640a47..60f75bf 100644 --- a/bsp/coreip-s51/README.md +++ b/bsp/coreip-s51/README.md @@ -4,6 +4,6 @@ This core target is suitable with Verilog RTL for verification and running appli - 1 hart with RV64IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels |