diff options
author | hsiang-chia.huang <hsiangchia.huang@sifive.com> | 2019-05-24 10:22:08 +0800 |
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committer | GitHub <noreply@github.com> | 2019-05-24 10:22:08 +0800 |
commit | faf58a49c3b6421107ada0e8af43170a5ffafcea (patch) | |
tree | 3996d52a748ae2420b5c9c6c9efe4158d5dece53 /bsp/coreip-u54mc-rtl/design.dts | |
parent | 7817c5e85cb6f9f6d5b98f6702fa4b7d1fb99e02 (diff) | |
parent | 2c0269905929128bd0bd13a55ae3d8afd60a1af6 (diff) |
Merge branch 'development-19.05' into dhrystone_19.05
Diffstat (limited to 'bsp/coreip-u54mc-rtl/design.dts')
-rw-r--r-- | bsp/coreip-u54mc-rtl/design.dts | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts index 27a3c94..2982dd5 100644 --- a/bsp/coreip-u54mc-rtl/design.dts +++ b/bsp/coreip-u54mc-rtl/design.dts @@ -5,6 +5,9 @@ #size-cells = <2>; compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev"; model = "SiFive,FU540G"; + chosen { + metal,boothart = <&L13>; + }; L36: cpus { #address-cells = <1>; #size-cells = <0>; @@ -18,6 +21,7 @@ next-level-cache = <&L33>; reg = <0x0>; riscv,isa = "rv64imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L7>; sifive,itim = <&L6>; status = "okay"; @@ -46,6 +50,7 @@ next-level-cache = <&L33>; reg = <0x1>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L11>; status = "okay"; timebase-frequency = <1000000>; @@ -74,6 +79,7 @@ next-level-cache = <&L33>; reg = <0x2>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L15>; status = "okay"; timebase-frequency = <1000000>; @@ -102,6 +108,7 @@ next-level-cache = <&L33>; reg = <0x3>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L19>; status = "okay"; timebase-frequency = <1000000>; @@ -130,6 +137,7 @@ next-level-cache = <&L33>; reg = <0x4>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L23>; status = "okay"; timebase-frequency = <1000000>; @@ -150,10 +158,6 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L30: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; |