Bump Everything to Match new Freedom Repo (#8)

* Bump tool versions

* Use version of OpenOCD which can load programs into flash

* Bump OpenOCD to Handle ISSI Flash Programming

* Update Header files

* add initial support for hifive1

* add dhrystone

* add clock helper functions

* add openocd cfg file

* Demo_GPIO checkpoint -- compiles and runs but no blinky LEDs

* Remove riscv-tests submodule

* Remove FPGA files, as they are no longer relevant to this Repository

* Add openocd_upload script

* Add Pinmux Mappings

Adding the pinmux mappings to the Platform Header

* Add IOF Mappings to platform header

* Re-order the IOF Mapping declarations

* Add more useful things to platform headers

* Get GPIO Demo working again (except interrupts aren't working)

* Update README with more OS packages needed

A bare ubuntu-16.04.1-server installation could not run `make tools`
without these packages.

* bump openocd to get SCKDIV fix

* Remove duplicated help text for run_debug target

* Add package to README that is needed for openocd build

Without this package I was seeing two different failures like below
when running `make tools`.

/home/scottj/freedom-e-sdk/openocd/configure: line 4533: syntax error near unexpected token `0.23'
/home/scottj/freedom-e-sdk/openocd/configure: line 4533: `PKG_PROG_PKG_CONFIG(0.23)'
Makefile:70: recipe for target '/home/scottj/freedom-e-sdk/toolchain/bin/openocd' failed
make: *** [/home/scottj/freedom-e-sdk/toolchain/bin/openocd] Error 2

... or ...

+ autoconf
configure.ac:12: error: possibly undefined macro: AC_MSG_WARN
      If this token and others are legitimate, please use m4_pattern_allow.
      See the Autoconf documentation.
configure.ac:240: error: possibly undefined macro: AC_MSG_NOTICE
configure.ac:342: error: possibly undefined macro: AC_DEFINE
Makefile:70: recipe for target '/home/scottj/freedom-e-sdk/toolchain/bin/openocd' failed
make: *** [/home/scottj/freedom-e-sdk/toolchain/bin/openocd] Error 1

* Bump OpenOCD to not overwrite SCKDIV when flashing

* Roll back CoreMark

1 files changed, 187 insertions, 0 deletions

diff --git a/bsp/env/freedom-e300-hifive1/init.c b/bsp/env/freedom-e300-hifive1/init.c
new file mode 100644
index 0000000..d085f6c
--- /dev/null
+++ b/bsp/env/freedom-e300-hifive1/init.c
@@ -0,0 +1,187 @@
+#include <stdint.h>
+#include <unistd.h>
+
+#include "platform.h"
+#include "encoding.h"
+
+uint32_t cpu_freq = 0;
+
+extern int main(int argc, char** argv);
+
+uint32_t mtime_lo(void)
+{
+  return *(volatile uint32_t *)(CLINT_BASE_ADDR + CLINT_MTIME);
+}
+
+uint32_t mcycle_lo(void)
+{
+  uint32_t t;
+  asm volatile ("csrr %0, mcycle" : "=r" (t));
+  return t;
+}
+
+static void use_hfrosc(int div, int trim)
+{
+  // Make sure the HFROSC is running at its default setting
+  PRCI_REG(PRCI_HFROSCCFG) = (ROSC_DIV(div) | ROSC_TRIM(trim) | ROSC_EN(1));
+  while ((PRCI_REG(PRCI_HFROSCCFG) & ROSC_RDY(1)) == 0) ;
+  PRCI_REG(PRCI_PLLCFG) &= ~PLL_SEL(1);
+}
+
+static void use_pll(int refsel, int bypass, int r, int f, int q)
+{
+  // Ensure that we aren't running off the PLL before we mess with it.
+  if (PRCI_REG(PRCI_PLLCFG) & PLL_SEL(1)) {
+    // Make sure the HFROSC is running at its default setting
+    use_hfrosc(4, 16);
+  }
+
+  // Set PLL Source to be HFXOSC if available.
+  uint32_t config_value = 0;
+
+  config_value |= PLL_REFSEL(refsel);
+
+  if (bypass) {
+    // Bypass
+    config_value |= PLL_BYPASS(1);
+
+    PRCI_REG(PRCI_PLLCFG) = config_value;
+
+    // If we don't have an HFXTAL, this doesn't really matter.
+    // Set our Final output divide to divide-by-1:
+    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+  } else {
+    // In case we are executing from QSPI,
+    // (which is quite likely) we need to
+    // set the QSPI clock divider appropriately
+    // before boosting the clock frequency.
+
+    // Div = f_sck/2
+    SPI0_REG(SPI_REG_SCKDIV) = 8;
+
+    // Set DIV Settings for PLL
+    // Both HFROSC and HFXOSC are modeled as ideal
+    // 16MHz sources (assuming dividers are set properly for
+    // HFROSC).
+    // (Legal values of f_REF are 6-48MHz)
+
+    // Set DIVR to divide-by-2 to get 8MHz frequency
+    // (legal values of f_R are 6-12 MHz)
+
+    config_value |= PLL_BYPASS(1);
+    config_value |= PLL_R(r);
+
+    // Set DIVF to get 512Mhz frequncy
+    // There is an implied multiply-by-2, 16Mhz.
+    // So need to write 32-1
+    // (legal values of f_F are 384-768 MHz)
+    config_value |= PLL_F(f);
+
+    // Set DIVQ to divide-by-2 to get 256 MHz frequency
+    // (legal values of f_Q are 50-400Mhz)
+    config_value |= PLL_Q(q);
+
+    // Set our Final output divide to divide-by-1:
+    PRCI_REG(PRCI_PLLDIV) = (PLL_FINAL_DIV_BY_1(1) | PLL_FINAL_DIV(0));
+
+    PRCI_REG(PRCI_PLLCFG) = config_value;
+
+    // Un-Bypass the PLL.
+    PRCI_REG(PRCI_PLLCFG) &= ~PLL_BYPASS(1);
+
+    // Wait for PLL Lock
+    // Note that the Lock signal can be glitchy.
+    // Need to wait 100 us
+    // RTC is running at 32kHz.
+    // So wait 4 ticks of RTC.
+    uint32_t now = mtime_lo();
+    while (mtime_lo() - now < 4) ;
+
+    // Now it is safe to check for PLL Lock
+    while ((PRCI_REG(PRCI_PLLCFG) & PLL_LOCK(1)) == 0) ;
+  }
+
+  // Switch over to PLL Clock source
+  PRCI_REG(PRCI_PLLCFG) |= PLL_SEL(1);
+}
+
+static void use_default_clocks()
+{
+  // Turn off the LFROSC
+  AON_REG(AON_LFROSC) &= ~ROSC_EN(1);
+
+  // Use HFROSC
+  use_hfrosc(4, 16);
+}
+
+void measure_cpu_freq(size_t n, size_t mtime_freq)
+{
+  uint32_t start_mtime = mtime_lo();
+  uint32_t start_mcycle = mcycle_lo();
+
+  while (mtime_lo() - start_mtime < n) ;
+
+  uint32_t end_mtime = mtime_lo();
+  uint32_t end_mcycle = mcycle_lo();
+
+  cpu_freq = (end_mcycle-start_mcycle)/n*mtime_freq;
+}
+
+uint32_t get_cpu_freq()
+{
+  return cpu_freq;
+}
+
+static void uart_init(size_t baud_rate)
+{
+  GPIO_REG(GPIO_IOF_SEL) &= ~IOF0_UART0_MASK;
+  GPIO_REG(GPIO_IOF_EN) |= IOF0_UART0_MASK;
+  UART0_REG(UART_REG_DIV) = get_cpu_freq() / baud_rate - 1;
+  UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
+}
+
+
+
+#ifdef USE_PLIC
+extern void handle_m_ext_interrupt();
+#endif
+
+#ifdef USE_M_TIME
+extern void handle_m_time_interrupt();
+#endif
+
+uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc)
+{
+  if (0){
+#ifdef USE_PLIC
+    // External Machine-Level interrupt from PLIC
+  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_EXT)) {
+    handle_m_ext_interrupt();
+#endif
+#ifdef USE_M_TIME
+    // External Machine-Level interrupt from PLIC
+  } else if ((mcause & MCAUSE_INT) && ((mcause & MCAUSE_CAUSE) == IRQ_M_TIMER)){
+    handle_m_time_interrupt();
+#endif
+  }
+  else {
+    write(1, "trap\n", 5);
+    _exit(1 + mcause);
+  }
+  return epc;
+}
+
+
+void _init()
+{
+  use_default_clocks();
+  use_pll(0, 0, 1, 31, 1);
+  measure_cpu_freq(1000, 32768);
+  uart_init(115200);
+
+  printf("core freq at %d Hz\n", get_cpu_freq());
+
+  write_csr(mtvec, &handle_trap);
+
+  _exit(main(0, NULL));
+}