diff options
| author | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-02-13 15:50:42 -0800 |
|---|---|---|
| committer | Nathaniel Graff <nathaniel.graff@sifive.com> | 2019-02-14 13:40:02 -0800 |
| commit | 32214436b103438abf4018b34e6c29bb71522249 (patch) | |
| tree | b3d437b8d391fb3e512b8ba4a58f80b711ebfc04 /bsp/sifive-hifive1 | |
| parent | fde5fd856378aed6c552fc0338e992f918dec18e (diff) | |
Add clocking and pinmux to the SPI on hifive1
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
Diffstat (limited to 'bsp/sifive-hifive1')
| -rw-r--r-- | bsp/sifive-hifive1/design.dts | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts index ff95ae0..5ddee6f 100644 --- a/bsp/sifive-hifive1/design.dts +++ b/bsp/sifive-hifive1/design.dts @@ -8,7 +8,7 @@ chosen { stdout-path = "/soc/serial@10013000:115200"; - metal,entry = <&sip0 0x400000>; + metal,entry = <&spi0 0x400000>; }; cpus { @@ -22,7 +22,7 @@ i-cache-block-size = <64>; i-cache-sets = <128>; i-cache-size = <16384>; - next-level-cache = <&sip0>; + next-level-cache = <&spi0>; reg = <0>; riscv,isa = "rv32imac"; sifive,dtim = <&dtim>; @@ -171,12 +171,14 @@ clocks = <&hfclk>; pinmux = <&gpio0 0x30000 0x30000>; }; - sip0: spi@10014000 { + spi0: spi@10014000 { compatible = "sifive,spi0"; interrupt-parent = <&plic>; interrupts = <6>; reg = <0x10014000 0x1000 0x20000000 0x20000000>; reg-names = "control", "mem"; + clocks = <&hfclk>; + pinmux = <&gpio0 0x0003C 0x0003C>; }; }; }; |